Quoting Miquel Raynal (2019-08-05 03:03:08) > From: Omri Itach <omrii@xxxxxxxxxxx> > > Add dynamic AP-DCLK clock (hclk) to system controller driver. AP-DCLK > is half the rate of DDR clock, so its derrived from Sample At Reset > configuration. The clock frequency is required for AP806 AXI monitor > profiling feature. > > Signed-off-by: Omri Itach <omrii@xxxxxxxxxxx> > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> > --- Applied to clk-next
