On Fri, 2019-08-16 at 17:09 +0200, Daniel Lezcano wrote: > On 31/07/2019 03:24, Atish Patra wrote: > > There is only one clocksource in RISC-V. The boot cpu initializes > > that clocksource. No need to keep a percpu data structure. > > That is not what is stated in the initial patch [1]. > > Can you clarify that ? > I think what I meant to say was "There is only one clocksource used in RISC-V Linux" as it is guranteed that all the timers across all the harts are synchronized within one tick of each other [2]. Apologies for not being verbose here. However, reading the privilege specification(1.12-draft) Section. 3.1.10 states that "Accurate real-time clocks (RTCs) are relatively expensive to provide (requiring a crystal or MEMS oscillator) and have to run even when the rest of system is powered down, and so there is usually only one in a system located in a different frequency/voltage domain from the processors. Hence, the RTC must be shared by all the harts in a system" This is different from the commit text in [1]. Perhaps I misunderstood something. @Palmer ? [2] https://elixir.bootlin.com/linux/v5.3-rc4/source/drivers/clocksource/timer-riscv.c#L44 > Thanks > > -- Daniel > > [1] https://lkml.org/lkml/2018/8/4/51 > > > > Signed-off-by: Atish Patra <atish.patra@xxxxxxx> > > --- > > drivers/clocksource/timer-riscv.c | 6 ++---- > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/clocksource/timer-riscv.c > > b/drivers/clocksource/timer-riscv.c > > index 5e6038fbf115..09e031176bc6 100644 > > --- a/drivers/clocksource/timer-riscv.c > > +++ b/drivers/clocksource/timer-riscv.c > > @@ -55,7 +55,7 @@ static u64 riscv_sched_clock(void) > > return get_cycles64(); > > } > > > > -static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { > > +static struct clocksource riscv_clocksource = { > > .name = "riscv_clocksource", > > .rating = 300, > > .mask = CLOCKSOURCE_MASK(64), > > @@ -92,7 +92,6 @@ void riscv_timer_interrupt(void) > > static int __init riscv_timer_init_dt(struct device_node *n) > > { > > int cpuid, hartid, error; > > - struct clocksource *cs; > > > > hartid = riscv_of_processor_hartid(n); > > if (hartid < 0) { > > @@ -112,8 +111,7 @@ static int __init riscv_timer_init_dt(struct > > device_node *n) > > > > pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", > > __func__, cpuid, hartid); > > - cs = per_cpu_ptr(&riscv_clocksource, cpuid); > > - error = clocksource_register_hz(cs, riscv_timebase); > > + error = clocksource_register_hz(&riscv_clocksource, > > riscv_timebase); > > if (error) { > > pr_err("RISCV timer register failed [%d] for cpu = > > [%d]\n", > > error, cpuid); > > > >
