Re: [PATCH] arm64: dts: allwinner: a64: Drop PMU node

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On 07/08/2019 03:39, Vasily Khoruzhick wrote:
On Tue, Aug 6, 2019 at 2:14 PM Robin Murphy <robin.murphy@xxxxxxx> wrote:

On 2019-08-06 9:52 pm, Vasily Khoruzhick wrote:
On Tue, Aug 6, 2019 at 1:19 PM Harald Geyer <harald@xxxxxxxxx> wrote:

Vasily Khoruzhick writes:
On Tue, Aug 6, 2019 at 7:35 AM Robin Murphy <robin.murphy@xxxxxxx> wrote:

On 06/08/2019 15:01, Vasily Khoruzhick wrote:
Looks like PMU in A64 is broken, it generates no interrupts at all and
as result 'perf top' shows no events.

Does something like 'perf stat sleep 1' at least count cycles correctly?
It could well just be that the interrupt numbers are wrong...

Looks like it does, at least result looks plausible:

I'm using perf stat regularly (cache benchmarks) and it works fine.

Unfortunately I wasn't aware that perf stat is a poor test for
the interrupts part of the node, when I added it. So I'm not too
surprised I got it wrong.

However, it would be unfortunate if the node got removed completely,
because perf stat would not work anymore. Maybe we can only remove
the interrupts or just fix them even if the HW doesn't work?

I'm not familiar with PMU driver. Is it possible to get it working
without interrupts?

Yup - you get a grumpy message from the driver, it will refuse sampling
events (the ones which weren't working anyway), and if you measure
anything for long enough that a counter overflows you'll get wonky
results. But for counting hardware events over relatively short periods
it'll still do the job.

I tried to drop interrupts completely from the node but 'perf top' is
still broken. Though now in different way: it complains "cycles: PMU
Hardware doesn't support sampling/overflow-interrupts. Try 'perf
stat'"

Is there any way to make it working?

As the message implies, 'perf top' can't work because it uses sampling events, which are based on periodic interrupts. If the IRQs aren't there, then too bad, as there's no alternative.

One other possibility is that the IRQs really are wired up, but the firmware is somehow leaving them configured as Secure group 0, such that Linux has no visibility of them.

Robin.



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