On Thu, May 30, 2019 at 6:45 AM <Anson.Huang@xxxxxxx> wrote:
> + gpio1: gpio@30200000 {
> + compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
> + reg = <0x30200000 0x10000>;
> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
No GPIO clocks entries?
> + usbphynop1: usbphynop1 {
> + compatible = "usb-nop-xceiv";
> + clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
> + assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
> + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
> + clock-names = "main_clk";
> + };
usbphynop1 does not have any registers associated, so it should be
placed outside the soc.
Building with W=1 should warn you about that.
> + usbphynop2: usbphynop2 {
> + compatible = "usb-nop-xceiv";
> + clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
> + assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
> + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
> + clock-names = "main_clk";
> + };
> +
Ditto
