From: Andreas Pretzsch <apr@xxxxxxxxx> Add support for the EDT ET035012DM6 3.5" 320x240 QVGA 24-bit RGB TFT. The datasheet with all specs can be retrieved online: https://www.glynshop.com/erp/owweb/Daten/DSS/EDT/Products/ \ Specifications/Active%20Displays/ET035012DM6.pdf Signed-off-by: Andreas Pretzsch <apr@xxxxxxxxx> [m.felsch@xxxxxxxxxxxxxx: adapt commit message] [m.felsch@xxxxxxxxxxxxxx: rm unecessary comments] [m.felsch@xxxxxxxxxxxxxx: correct data_enable polarity] Signed-off-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx> --- drivers/gpu/drm/panel/panel-simple.c | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 8fee7a8b29d9..b4ead9cf3d14 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -1096,6 +1096,32 @@ static const struct panel_desc dlc_dlc1010gig = { .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, }; +static const struct drm_display_mode edt_et035012dm6_mode = { + .clock = 6500, + .hdisplay = 320, + .hsync_start = 320 + 20, + .hsync_end = 320 + 20 + 30, + .htotal = 320 + 20 + 68, + .vdisplay = 240, + .vsync_start = 240 + 4, + .vsync_end = 240 + 4 + 4, + .vtotal = 240 + 4 + 4 + 14, + .vrefresh = 60, + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, +}; + +static const struct panel_desc edt_et035012dm6 = { + .modes = &edt_et035012dm6_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 70, + .height = 52, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE, +}; + static const struct drm_display_mode edt_et057090dhu_mode = { .clock = 25175, .hdisplay = 640, @@ -2645,6 +2671,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "dlc,dlc1010gig", .data = &dlc_dlc1010gig, + }, { + .compatible = "edt,et035012dm6", + .data = &edt_et035012dm6, }, { .compatible = "edt,et057090dhu", .data = &edt_et057090dhu, -- 2.20.1
