On Mon, 15 Apr 2019 at 14:24, Anand Moon <linux.amoon@xxxxxxxxx> wrote: > Cache Coherent Interface (CCI) among Cortex-A15 and Cortex-A7, G2D, G3D and SSS > > Level 0 > CPU blocks such as Cortex-A15 (CA15), Cortex-A7 (CA7) are > joined as the member of Level 0 CCI bus > > Level 1 > Display engine block (DISP) and 2D graphic engines (G2D) are > directly connected to Level 1. > DISP, MDMA, SSS. > > Level 2 > While all the other IP is connected to Level 1 bus via Level 2 bus > G3D, MSCL, MFC, ISP, JPEG/Rotator/DMA/PERI, NAND/SD/EMMC. > > So my question is the mapped with the cci ip block correct. > Level 0 (cci_control0) > Level 1 (cci_control1) > Level 2 (cci_control1) Hi Anand, I do not understand the question - what is mapped with correctly or not? Best regards, Krzysztof
