On Fri, Mar 22, 2019 at 08:45:26AM -0400, Gaël PORTAY wrote: > Hi Matthias, > > On Thu, Mar 21, 2019 at 05:01:07PM -0700, Matthias Kaehlcke wrote: > > > ... > > > > > > So, for a reason that I ignore, if we try to save unecessary calls to > > > ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD (odt_enable has not changed since > > > last call), we get stalled in the call to ROCKCHIP_SIP_CONFIG_SET_RAGE > > > that follows. The function arm_smccc_smc never returns and the device > > > hard hang. > > > > Thanks for giving it a try! > > > > Did your code ensure to perform the SMC call for the first frequency > > change? If not the problem could be that the DDR PD timings and ODT > > resistors are not properly configured for the new frequency. > > > > The DRAM_ODT_PD SMC call is supposed to be performed before the > DRAM_SET_RATE; unless someone else is doing the set_rate. However earlier the call wasn't done at all, and that didn't cause problems. > Does the ODT resistors should be configured for every existing > frequency? I don't have any background here. My initial assumption would be that it should be enough to re-configure them when the frequency passes the threshold in either direction. Anyway, IIUC there shouldn't be more than 5 frequency changes per second (polling_ms = 200), and likely no all of them would pass the threshold, so it seems limiting the calls (if possible) would be a micro-optimization and is probably not worth the hassle :) Thanks Matthias
