Hi Matthias, On Thu, Mar 21, 2019 at 05:01:07PM -0700, Matthias Kaehlcke wrote: > > ... > > > > So, for a reason that I ignore, if we try to save unecessary calls to > > ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD (odt_enable has not changed since > > last call), we get stalled in the call to ROCKCHIP_SIP_CONFIG_SET_RAGE > > that follows. The function arm_smccc_smc never returns and the device > > hard hang. > > Thanks for giving it a try! > > Did your code ensure to perform the SMC call for the first frequency > change? If not the problem could be that the DDR PD timings and ODT > resistors are not properly configured for the new frequency. > The DRAM_ODT_PD SMC call is supposed to be performed before the DRAM_SET_RATE; unless someone else is doing the set_rate. Does the ODT resistors should be configured for every existing frequency? > In case you already did this or it doesn't help I think it's fine to > just do the call always, we can always revisit this later. > Okay, sounds good. > > Thanks to your remark, I have also fixed an issue with the odt_dis_freq > > value. Its value is initialized to 0 in the probe function. Thus the > > odt_enable is always true (target_rate > 0). I moved its initialization > > after the timings are parsed from the device-tree; its value is now none > > zero (333000000 in my case). > > Great! Gael
