> From: Rob Herring [mailto:robh@xxxxxxxxxx] > Sent: Tuesday, January 22, 2019 8:10 AM > > On Fri, Jan 11, 2019 at 11:56:09AM +0000, Aisheng Dong wrote: > > Add a53 and a72 clock id, as there's still no users, we update > > IMX_LSIO_MEM_CLK base to start from 6 to allow a53 and a72 clock id to > > be continued with a35 clk. > > > > Cc: Stephen Boyd <sboyd@xxxxxxxxxx> > > Cc: Rob Herring <robh+dt@xxxxxxxxxx> > > Cc: devicetree@xxxxxxxxxxxxxxx > > Cc: Shawn Guo <shawnguo@xxxxxxxxxx> > > Cc: Sascha Hauer <kernel@xxxxxxxxxxxxxx> > > Cc: Fabio Estevam <fabio.estevam@xxxxxxx> > > Cc: Michael Turquette <mturquette@xxxxxxxxxxxx> > > Signed-off-by: Dong Aisheng <aisheng.dong@xxxxxxx> > > --- > > include/dt-bindings/clock/imx8-clock.h | 6 ++++-- > > 1 file changed, 4 insertions(+), 2 deletions(-) > > > > diff --git a/include/dt-bindings/clock/imx8-clock.h > > b/include/dt-bindings/clock/imx8-clock.h > > index 4236818..2f1aa2f 100644 > > --- a/include/dt-bindings/clock/imx8-clock.h > > +++ b/include/dt-bindings/clock/imx8-clock.h > > @@ -13,10 +13,12 @@ > > > > /* CPU */ > > #define IMX_A35_CLK 1 > > +#define IMX_A53_CLK 2 > > +#define IMX_A72_CLK 3 > > All 3 cores in one chip? If not maybe these should be split or define them as > cpu cluster x clocks. > Not in one chip. Here are common clock IDs used for both MX8QXP and MX8QM. You mean change to something like below? #define IMX_CPU_CLUSTER_A53_CLK 2 #define IMX_CPU_CLUSTER_A72_CLK 3 Regards Dong Aisheng > > > > /* LSIO SS */ > > -#define IMX_LSIO_MEM_CLK 2 > > -#define IMX_LSIO_BUS_CLK 3 > > +#define IMX_LSIO_MEM_CLK 6 > > +#define IMX_LSIO_BUS_CLK 7 > > #define IMX_LSIO_PWM0_CLK 10 > > #define IMX_LSIO_PWM1_CLK 11 > > #define IMX_LSIO_PWM2_CLK 12 > > -- > > 2.7.4 > >
