On Tue, Jan 22, 2019 at 6:59 AM Aisheng Dong <aisheng.dong@xxxxxxx> wrote: > > > From: Rob Herring [mailto:robh@xxxxxxxxxx] > > Sent: Tuesday, January 22, 2019 8:10 AM > > > > On Fri, Jan 11, 2019 at 11:56:09AM +0000, Aisheng Dong wrote: > > > Add a53 and a72 clock id, as there's still no users, we update > > > IMX_LSIO_MEM_CLK base to start from 6 to allow a53 and a72 clock id to > > > be continued with a35 clk. > > > > > > Cc: Stephen Boyd <sboyd@xxxxxxxxxx> > > > Cc: Rob Herring <robh+dt@xxxxxxxxxx> > > > Cc: devicetree@xxxxxxxxxxxxxxx > > > Cc: Shawn Guo <shawnguo@xxxxxxxxxx> > > > Cc: Sascha Hauer <kernel@xxxxxxxxxxxxxx> > > > Cc: Fabio Estevam <fabio.estevam@xxxxxxx> > > > Cc: Michael Turquette <mturquette@xxxxxxxxxxxx> > > > Signed-off-by: Dong Aisheng <aisheng.dong@xxxxxxx> > > > --- > > > include/dt-bindings/clock/imx8-clock.h | 6 ++++-- > > > 1 file changed, 4 insertions(+), 2 deletions(-) > > > > > > diff --git a/include/dt-bindings/clock/imx8-clock.h > > > b/include/dt-bindings/clock/imx8-clock.h > > > index 4236818..2f1aa2f 100644 > > > --- a/include/dt-bindings/clock/imx8-clock.h > > > +++ b/include/dt-bindings/clock/imx8-clock.h > > > @@ -13,10 +13,12 @@ > > > > > > /* CPU */ > > > #define IMX_A35_CLK 1 > > > +#define IMX_A53_CLK 2 > > > +#define IMX_A72_CLK 3 > > > > All 3 cores in one chip? If not maybe these should be split or define them as > > cpu cluster x clocks. > > > > Not in one chip. > Here are common clock IDs used for both MX8QXP and MX8QM. > You mean change to something like below? > > #define IMX_CPU_CLUSTER_A53_CLK 2 > #define IMX_CPU_CLUSTER_A72_CLK 3 What happened to A35? What I'm saying is if the same clock controller registers are used across chips even if the cores are different, use the same clock ID. Ideally, clock IDs have some relationship to the h/w such as their control register address and offset. To put it another way, don't create a common number space of clock IDs across SoCs unless they are strictly subsets and supersets of each other. Rob
