On Tue, 2017-04-04 at 12:32 -0500, Christopher Bostic wrote: > Agreed that there is room for improvement. I intend to look further > into your suggestions from here and our private conversation on the > matter and make changes as appropriate. I have an open issue to track > this. As it exists in this patch reads/writes from master to slave > fundamentally work. My understanding is they "seem to work if you get lucky with the timing and fall apart under load". Or did I hear wrong ? > Given the pervasiveness and time to fully evaluate > and test any protocol updates I intend address this in the near future > with a separate follow on patch. Please try the simple change I proposed in my email. It's a 4 or 5 lines change max to your clock_toggle function and how it's called in send and receive. It should be trivial to check if things still "seem to work" to begin with. Do you have some kind of test mechanism that hammers the FSI continuously ? Such as doing a series of putmemproc/getmemproc & checking the values ? Then you can run that while hammering the LPC bus and generally putting the BMC under load and you'll quickly see if it's reliable or not. Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
