On 21.2.2017 16:39, Anatolij Gustschin wrote:
> On Tue, 21 Feb 2017 16:27:34 +0100
> Michal Simek michal.simek@xxxxxxxxxx wrote:
> ...
>> ok. That means only dout (din fpga) and clk out (fpga clk in) and gpio
>> handling for others signals.
>
> yes, exactly.
>
> ...
>>> Usage example for full FPGA configuration:
>>>
>>> fpga-region0 {
>>> compatible = "fpga-region";
>>> fpga-mgr = <&fpga_mgr_spi>;
>>> #address-cells = <0x1>;
>>> #size-cells = <0x1>;
>>> };
>>>
>>> &spi1 {
>>> status = "okay";
>>>
>>> fpga_mgr_spi: fpga-mgr@0 {
>>> compatible = "xlnx,fpga-slave-serial";
>>> reg = <0>;
>>> spi-max-frequency = <60000000>;
>>> spi-cpha;
>>> done-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
>>> prog_b-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
>>> };
>>> };
>>
>> Right I would even replace &spi1 with full node to see content but this
>> is also good.
>
> Okay, will add in patch v3.
There is one thing I have checked ml505 - old virtex 5 board which has
this interface.
http://www-inst.eecs.berkeley.edu/~cs150/fa13/resources/ml50x_schematics.pdf
And I was chatting with one board guy and I think that done pin should
be optional not required because not all boards export it.
Then there is a question how to find out that programming was done and
that's something what I don't know. But will try to find out if you can
send any sequence over spi to find it out instead of gpio done pin.
Thanks,
Michal
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