Shawn, On Wed, Jun 8, 2016 at 12:25 AM, Shawn Lin <shawn.lin@xxxxxxxxxxxxxx> wrote: > This patch adds a binding that describes the Rockchip PCIe PHY > found on Rockchip SoCs PCIe interface. > > Signed-off-by: Shawn Lin <shawn.lin@xxxxxxxxxxxxxx> > --- > > .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt > > diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt > new file mode 100644 > index 0000000..ba8c406 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt > @@ -0,0 +1,22 @@ > +Rockchip PCIE PHY > +----------------------- > + > +Required properties: > + - compatible: rockchip,rk3399-pcie-phy > + - #phy-cells: must be 0 Code also requires reset and clock. clocks = <&cru SCLK_PCIEPHY_REF>; clock-names = "refclk"; resets = <&cru SRST_PCIEPHY>; reset-names = "phy"; -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
