This patch adds a binding that describes the Rockchip PCIe PHY
found on Rockchip SoCs PCIe interface.
Signed-off-by: Shawn Lin <shawn.lin@xxxxxxxxxxxxxx>
---
.../devicetree/bindings/phy/rockchip-pcie-phy.txt | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
new file mode 100644
index 0000000..ba8c406
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
@@ -0,0 +1,22 @@
+Rockchip PCIE PHY
+-----------------------
+
+Required properties:
+ - compatible: rockchip,rk3399-pcie-phy
+ - #phy-cells: must be 0
+
+Example:
+
+grf: syscon@ff770000 {
+ compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ...
+
+ pcie_phy: phy@e220 {
+ compatible = "rockchip,rk3399-pcie-phy";
+ #phy-cells = <0>;
+ };
+};
+
--
2.3.7
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