On Wed, 2016-04-27 at 14:50 +0100, Mark Brown wrote: > On Wed, Apr 27, 2016 at 04:53:18AM +0900, Akinobu Mita wrote: > > > > > For the read data transfer, the address/command byte is sent on the > > rising edge of the first eight SCLK cycles and the read data byte > > is > > transmitted on the falling edge of the next eight SCL cycles. > That's an innovative and exciting hardware design :/ Definitely > doesn't > seem to correspond too closely to any SPI mode I can think of. DS1302 uses the standard MicroWire half-duplex transfer timing. The timing can be handled by eg. PXA270 built-in SPI controller with proper configuration. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
