On Wed, Apr 27, 2016 at 04:53:18AM +0900, Akinobu Mita wrote: > For the read data transfer, the address/command byte is sent on the > rising edge of the first eight SCLK cycles and the read data byte is > transmitted on the falling edge of the next eight SCL cycles. That's an innovative and exciting hardware design :/ Definitely doesn't seem to correspond too closely to any SPI mode I can think of.
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