Sorry for the late reply. 2016-04-12 10:25 GMT+09:00 Mark Brown <broonie@xxxxxxxxxx>: > On Sun, Apr 10, 2016 at 05:38:55PM +0200, Alexandre Belloni wrote: >> On 10/04/2016 at 18:23:01 +0300, Sergei Ianovich wrote : > >> > No, unfortunately. I've investigated this possibility for my platform. >> > spi-gpio doesn't support LSB-first and 3-wire options. Adding support >> > there is a very big change. The best way to add GPIO support is to >> > create spi-gpio-3wire with LSB-first support. > >> Mark, do you have nay opinion on that? > > Three wire doesn't seem like it should be invasive, LSB is going to be a > lot more invasive though it seems reasonable to just do the reversal in > the driver for whatever device this is and let the SPI controller run > normally. Or we could do that in the core with a pass over the data. I've added 3wire support to spi-gpio and added the bit reversal logic to ds1302 driver if the spi mode is not LSB first. But the register read command doesn't work. I think there is no suitable SPI mode that can communicate with DS1302. The reason is as follows. For the read data transfer, the address/command byte is sent on the rising edge of the first eight SCLK cycles and the read data byte is transmitted on the falling edge of the next eight SCL cycles. But in the latter read data byte data phase, I/O pin is tri-stated upon each rising edge of SCLK. (Please see DATA OUTPUT section and Figure 6. Timing Diagram: Read Data Transfer in https://datasheets.maximintegrated.com/en/ds/DS1302.pdf) So if the SPI mode 0 (CPOL=0 CPHA=0) is selected, the address/command byte phase is ok but the read data byte is unavailable because each bit is retrieved while SCLK is high. Similarly there is no suitable SPI mode for DS1302. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
