On 10/30, Kumar Gala wrote: > > On Oct 30, 2013, at 4:58 PM, Stephen Boyd wrote: > > > On 10/30/13 14:56, Kumar Gala wrote: > >> On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote: > >> > >>> On 10/30/13 14:45, Kumar Gala wrote: > >>>> On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote: > >>>>> +l2-cache node containing the following properties: > >>>> Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)? > >>> Yes it is per CPU. That is what the 0xf part of the cpus interrupts > >>> property is showing. > >> Than why not have it in each cpu node? > > > > Because that duplicates things unnecessarily? The cpus node can hold > > things that are common to all CPUs to avoid duplication. If it was a > > different PPI for each CPU then I would agree that we need to put it in > > each cpu node. > > Ok, I'll accept that as the binding is specific to Krait (and I assume all SoCs w/Krait wire this up to a common interrupt) > Can I take that as an ack? I'll resend with the s/an/a/ fix today. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
