On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote:
> On 10/30/13 14:45, Kumar Gala wrote:
>> On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote:
>>
>>> @@ -75,3 +77,50 @@ Example:
>>> reg = <0x101>;
>>> };
>>> };
>>> +
>>> +If the compatible string contains "qcom,krait" there shall be an interrupts
>>> +property containing the L1/CPU error interrupt number. There shall also be an
>> 'also be a'
>
> ok
>
>>
>>> +l2-cache node containing the following properties:
>> Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)?
>
> Yes it is per CPU. That is what the 0xf part of the cpus interrupts
> property is showing.
Than why not have it in each cpu node?
>>>
>>> + - compatible: Shall contain at least "cache"
>>> + - cache-level: Must be 2
>>> + - interrupts: Shall contain the L2 error interrupt
>>> +
>>> +Example:
>>> +
>>> + cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + interrupts = <1 9 0xf04>;
>>> + compatible = "qcom,krait";
>>>
- k
--
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