> -----Original Message-----
> From: Wood Scott-B07421
> Sent: 2013年9月12日 星期四 9:10
> To: Tang Yuantian-B29983
> Cc: galak@xxxxxxxxxxxxxxxxxxx; linuxppc-dev@xxxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; Li Yang-Leo-R58472
> Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree
> nodes
>
> On Wed, 2013-09-11 at 14:57 +0800, Yuantian.Tang@xxxxxxxxxxxxx wrote:
> > From: Tang Yuantian <yuantian.tang@xxxxxxxxxxxxx>
> >
> > The following SoCs will be affected: p2041, p3041, p4080, p5020,
> > p5040, b4420, b4860, t4240
> >
> > Signed-off-by: Tang Yuantian <Yuantian.Tang@xxxxxxxxxxxxx>
> > Signed-off-by: Li Yang <leoli@xxxxxxxxxxxxx>
> > ---
> > v4:
> > - add binding document
> > - update compatible string
> > - update the reg property
> > v3:
> > - fix typo
> > v2:
> > - add t4240, b4420, b4860 support
> > - remove pll/4 clock from p2041, p3041 and p5020 board
> >
> > .../devicetree/bindings/clock/corenet-clock.txt | 80
> +++++++++++++++
> > arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 34 ++++++-
> > arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 2 +
> > arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 34 ++++++-
> > arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 4 +
> > arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 59 ++++++++++-
> > arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | 4 +
> > arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 59 ++++++++++-
> > arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi | 4 +
> > arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 111
> ++++++++++++++++++++-
> > arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi | 8 ++
> > arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 41 +++++++-
> > arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | 2 +
> > arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 59 ++++++++++-
> > arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi | 4 +
> > arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 84
> +++++++++++++++-
> > arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 12 +++
> > 17 files changed, 593 insertions(+), 8 deletions(-) create mode
> > 100644 Documentation/devicetree/bindings/clock/corenet-clock.txt
> >
> > diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt
> > b/Documentation/devicetree/bindings/clock/corenet-clock.txt
> > new file mode 100644
> > index 0000000..51eab75
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt
> > @@ -0,0 +1,80 @@
> > +Device Tree Clock bindings for Freescale PowerPC corenet platform
> > +
> > +This binding uses the common clock binding[1].
> > +
> > +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> > +
> > +Required properties:
> > +- compatible : shall be one or more of the following:
>
> Shall include...
>
> > + - "fsl,<chip>-clockgen": for chip specific clock block
> > + - "fsl,qoriq-clockgen-[1,2].0": for chassis 1.0 and 2.0 clock
> > + block respectively.
> > + - "fsl,qoriq-chassis[1,2]-core-pll" - for a core PLL clock
> > + - "fsl,qoriq-chassis[1,2]-core-mux" - for a core multiplexer clock.
> > + Divided from the core PLL clock
>
> Hmm, there's a bit of a mismatch here between "chassis2" and the "2.0"
> on the clockgen node... perhaps it should be "fsl,qoriq-core-pll-2.0",
> etc.
>
> > + - "fixed-clock" - from common clock binding; should be output clock
> > + of oscillator
> > +- reg : shall be the control register offset from clock block base
> address.
>
> This description of "reg" is overly specific (assumes how the parent
> node's ranges are set up), incomplete (there's a size as well as the
> offset), and does not apply to the clockgen node itself (you probably
> shouldn't lump them together like this).
>
Do you mean I should explain the REG of clockgen and its child node respectively?
> > +- clocks : shall be the input parent clock phandle for the clock.
>
> Not required on the clockgen node
>
Required by child node of clockgen.
Regards,
Yuantian
> -Scott
>
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