On Mon, Jun 24, 2019 at 8:37 PM Paul Walmsley <paul.walmsley@xxxxxxxxxx> wrote:
>
> These two patches add a common "cpus" schema. They pass
> dt-doc-validate as of commit 2550ac333f6ed4ceb1e785262c54ec8619df077a
> ("meta-schemas: Allow additional keys under node properties").
Now we get a bunch of warnings because the examples are now validated
(in next) against the schemas.
Documentation/devicetree/bindings/arm/cpus.example.dt.yaml:
cpu@0:compatible:0: 'arm,cortex-a15' is not one of ['sifive,rocket0',
'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
Documentation/devicetree/bindings/arm/cpus.example.dt.yaml:
cpu@0:compatible: ['arm,cortex-a15'] is too short
Documentation/devicetree/bindings/arm/cpus.example.dt.yaml: cpu@0:
'riscv,isa' is a required property
Documentation/devicetree/bindings/arm/cpus.example.dt.yaml: cpu@0:
'timebase-frequency' is a required property
Documentation/devicetree/bindings/arm/cpus.example.dt.yaml: cpu@0:
'interrupt-controller' is a required property
Documentation/devicetree/bindings/arm/cpus.example.dt.yaml:
'cache-level' is a required property
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml:
cpu@0:compatible:0: 'sifive,rocket0' is not one of ['arm,arm710t',
'arm,arm720t', 'arm,arm740t', 'arm,arm7ej-s', 'arm,arm7tdmi',
'arm,arm7tdmi-s', 'arm,arm9es', 'arm,arm9ej-s', 'arm,arm920t',
'arm,arm922t', 'arm,arm925', 'arm,arm926e-s', 'arm,arm926ej-s',
'arm,arm940t', 'arm,arm946e-s', 'arm,arm966e-s', 'arm,arm968e-s',
'arm,arm9tdmi', 'arm,arm1020e', 'arm,arm1020t', 'arm,arm1022e',
'arm,arm1026ej-s', 'arm,arm1136j-s', 'arm,arm1136jf-s',
'arm,arm1156t2-s', 'arm,arm1156t2f-s', 'arm,arm1176jzf',
'arm,arm1176jz-s', 'arm,arm1176jzf-s', 'arm,arm11mpcore', 'arm,armv8',
'arm,cortex-a5', 'arm,cortex-a7', 'arm,cortex-a8', 'arm,cortex-a9',
'arm,cortex-a12', 'arm,cortex-a15', 'arm,cortex-a17',
'arm,cortex-a53', 'arm,cortex-a57', 'arm,cortex-a72',
'arm,cortex-a73', 'arm,cortex-m0', 'arm,cortex-m0+', 'arm,cortex-m1',
'arm,cortex-m3', 'arm,cortex-m4', 'arm,cortex-r4', 'arm,cortex-r5',
'arm,cortex-r7', 'brcm,brahma-b15', 'brcm,brahma-b53', 'brcm,vulcan',
'cavium,thunder', 'cavium,thunder2', 'faraday,fa526', 'intel,sa110',
'intel,sa1100', 'marvell,feroceon', 'marvell,mohawk', 'marvell,pj4a',
'marvell,pj4b', 'marvell,sheeva-v5', 'marvell,sheeva-v7',
'nvidia,tegra132-denver', 'nvidia,tegra186-denver',
'nvidia,tegra194-carmel', 'qcom,krait', 'qcom,kryo', 'qcom,kryo385',
'qcom,scorpion']
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml:
cpu@0:compatible:1: 'riscv' is not one of ['arm,arm710t',
'arm,arm720t', 'arm,arm740t', 'arm,arm7ej-s', 'arm,arm7tdmi',
'arm,arm7tdmi-s', 'arm,arm9es', 'arm,arm9ej-s', 'arm,arm920t',
'arm,arm922t', 'arm,arm925', 'arm,arm926e-s', 'arm,arm926ej-s',
'arm,arm940t', 'arm,arm946e-s', 'arm,arm966e-s', 'arm,arm968e-s',
'arm,arm9tdmi', 'arm,arm1020e', 'arm,arm1020t', 'arm,arm1022e',
'arm,arm1026ej-s', 'arm,arm1136j-s', 'arm,arm1136jf-s',
'arm,arm1156t2-s', 'arm,arm1156t2f-s', 'arm,arm1176jzf',
'arm,arm1176jz-s', 'arm,arm1176jzf-s', 'arm,arm11mpcore', 'arm,armv8',
'arm,cortex-a5', 'arm,cortex-a7', 'arm,cortex-a8', 'arm,cortex-a9',
'arm,cortex-a12', 'arm,cortex-a15', 'arm,cortex-a17',
'arm,cortex-a53', 'arm,cortex-a57', 'arm,cortex-a72',
'arm,cortex-a73', 'arm,cortex-m0', 'arm,cortex-m0+', 'arm,cortex-m1',
'arm,cortex-m3', 'arm,cortex-m4', 'arm,cortex-r4', 'arm,cortex-r5',
'arm,cortex-r7', 'brcm,brahma-b15', 'brcm,brahma-b53', 'brcm,vulcan',
'cavium,thunder', 'cavium,thunder2', 'faraday,fa526', 'intel,sa110',
'intel,sa1100', 'marvell,feroceon', 'marvell,mohawk', 'marvell,pj4a',
'marvell,pj4b', 'marvell,sheeva-v5', 'marvell,sheeva-v7',
'nvidia,tegra132-denver', 'nvidia,tegra186-denver',
'nvidia,tegra194-carmel', 'qcom,krait', 'qcom,kryo', 'qcom,kryo385',
'qcom,scorpion']
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml:
cpu@0:compatible: ['sifive,rocket0', 'riscv'] is too long
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml:
cpu@1:compatible:0: 'sifive,rocket0' is not one of ['arm,arm710t',
'arm,arm720t', 'arm,arm740t', 'arm,arm7ej-s', 'arm,arm7tdmi',
'arm,arm7tdmi-s', 'arm,arm9es', 'arm,arm9ej-s', 'arm,arm920t',
'arm,arm922t', 'arm,arm925', 'arm,arm926e-s', 'arm,arm926ej-s',
'arm,arm940t', 'arm,arm946e-s', 'arm,arm966e-s', 'arm,arm968e-s',
'arm,arm9tdmi', 'arm,arm1020e', 'arm,arm1020t', 'arm,arm1022e',
'arm,arm1026ej-s', 'arm,arm1136j-s', 'arm,arm1136jf-s',
'arm,arm1156t2-s', 'arm,arm1156t2f-s', 'arm,arm1176jzf',
'arm,arm1176jz-s', 'arm,arm1176jzf-s', 'arm,arm11mpcore', 'arm,armv8',
'arm,cortex-a5', 'arm,cortex-a7', 'arm,cortex-a8', 'arm,cortex-a9',
'arm,cortex-a12', 'arm,cortex-a15', 'arm,cortex-a17',
'arm,cortex-a53', 'arm,cortex-a57', 'arm,cortex-a72',
'arm,cortex-a73', 'arm,cortex-m0', 'arm,cortex-m0+', 'arm,cortex-m1',
'arm,cortex-m3', 'arm,cortex-m4', 'arm,cortex-r4', 'arm,cortex-r5',
'arm,cortex-r7', 'brcm,brahma-b15', 'brcm,brahma-b53', 'brcm,vulcan',
'cavium,thunder', 'cavium,thunder2', 'faraday,fa526', 'intel,sa110',
'intel,sa1100', 'marvell,feroceon', 'marvell,mohawk', 'marvell,pj4a',
'marvell,pj4b', 'marvell,sheeva-v5', 'marvell,sheeva-v7',
'nvidia,tegra132-denver', 'nvidia,tegra186-denver',
'nvidia,tegra194-carmel', 'qcom,krait', 'qcom,kryo', 'qcom,kryo385',
'qcom,scorpion']
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml:
cpu@1:compatible:1: 'riscv' is not one of ['arm,arm710t',
'arm,arm720t', 'arm,arm740t', 'arm,arm7ej-s', 'arm,arm7tdmi',
'arm,arm7tdmi-s', 'arm,arm9es', 'arm,arm9ej-s', 'arm,arm920t',
'arm,arm922t', 'arm,arm925', 'arm,arm926e-s', 'arm,arm926ej-s',
'arm,arm940t', 'arm,arm946e-s', 'arm,arm966e-s', 'arm,arm968e-s',
'arm,arm9tdmi', 'arm,arm1020e', 'arm,arm1020t', 'arm,arm1022e',
'arm,arm1026ej-s', 'arm,arm1136j-s', 'arm,arm1136jf-s',
'arm,arm1156t2-s', 'arm,arm1156t2f-s', 'arm,arm1176jzf',
'arm,arm1176jz-s', 'arm,arm1176jzf-s', 'arm,arm11mpcore', 'arm,armv8',
'arm,cortex-a5', 'arm,cortex-a7', 'arm,cortex-a8', 'arm,cortex-a9',
'arm,cortex-a12', 'arm,cortex-a15', 'arm,cortex-a17',
'arm,cortex-a53', 'arm,cortex-a57', 'arm,cortex-a72',
'arm,cortex-a73', 'arm,cortex-m0', 'arm,cortex-m0+', 'arm,cortex-m1',
'arm,cortex-m3', 'arm,cortex-m4', 'arm,cortex-r4', 'arm,cortex-r5',
'arm,cortex-r7', 'brcm,brahma-b15', 'brcm,brahma-b53', 'brcm,vulcan',
'cavium,thunder', 'cavium,thunder2', 'faraday,fa526', 'intel,sa110',
'intel,sa1100', 'marvell,feroceon', 'marvell,mohawk', 'marvell,pj4a',
'marvell,pj4b', 'marvell,sheeva-v5', 'marvell,sheeva-v7',
'nvidia,tegra132-denver', 'nvidia,tegra186-denver',
'nvidia,tegra194-carmel', 'qcom,krait', 'qcom,kryo', 'qcom,kryo385',
'qcom,scorpion']
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml:
cpu@1:compatible: ['sifive,rocket0', 'riscv'] is too long
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0:
'timebase-frequency' is a required property
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml:
'cache-level' is a required property
The main problem is the Arm cpu schema is applied on RiscV nodes and
vice-versa. I think since we have the common cpus schema now, we'll
need to remove the 'cpus' node from the riscv and arm schemas so we
only apply the schema on matching compatibles. The last one here is
probably from cache-controller.yaml.
And then these are just from dtc which you should have seen already:
Documentation/devicetree/bindings/riscv/cpus.example.dts:75.25-35:
Warning (reg_format): /example-1/cpus/cpu@0:reg: property has invalid
length (4 bytes) (#address-cells == 2, #size-cells == 1)
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: Warning
(pci_device_bus_num): Failed prerequisite 'reg_format'
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: Warning
(i2c_bus_reg): Failed prerequisite 'reg_format'
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: Warning
(spi_bus_reg): Failed prerequisite 'reg_format'
Documentation/devicetree/bindings/riscv/cpus.example.dts:73.23-84.19:
Warning (avoid_default_addr_size): /example-1/cpus/cpu@0: Relying on
default #address-cells value
Documentation/devicetree/bindings/riscv/cpus.example.dts:73.23-84.19:
Warning (avoid_default_addr_size): /example-1/cpus/cpu@0: Relying on
default #size-cells value
Rob
