[PATCH 2/2] schemas: add "cpus" schema

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Add an initial "cpus" schema, requested by Rob Herring.  This is based
on the Devicetree specification 0.2 at:

https://github.com/devicetree-org/devicetree-specification/releases/tag/v0.2

There are a few differences: this document is more tolerant than the
specification.  For example, POWER-specific properties are not
included, since those seem better served by POWER-specific DT binding
documents, rather than a generic document.  This binding also
tolerates the absence of some properties that are not required in
practice, such as the "clock-frequency" property.

This second version incorporates changes based on feedback from Rob
Herring <robh@xxxxxxxxxx>.

Signed-off-by: Paul Walmsley <paul.walmsley@xxxxxxxxxx>
Cc: Rob Herring <robh@xxxxxxxxxx>
---
 schemas/cpus.yaml | 147 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)
 create mode 100644 schemas/cpus.yaml

diff --git a/schemas/cpus.yaml b/schemas/cpus.yaml
new file mode 100644
index 0000000..06e54c4
--- /dev/null
+++ b/schemas/cpus.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-clause
+# Copyright (C) 2018-2019 SiFive, Inc.
+#
+# Description text is from the Devicetree Specification at
+#   https://www.devicetree.org/specifications/
+# which is
+# Copyright 2008,2011 Power.org, Inc.
+# Copyright 2008,2011 Freescale Semiconductor, Inc.
+# Copyright 2008,2011 International Business Machines Corporation
+# Copyright 2016,2017 Linaro,Ltd.
+# Copyright 2016,2017 Arm,Ltd.
+#
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/base.yaml#
+
+title: Common cpus binding
+
+maintainers:
+  - Devicetree Specification Mailing List <devicetree-spec@xxxxxxxxxxxxxxx>
+
+description: |+
+  In Devicetree data files, the layout of CPUs is described in the
+  "cpus" node.  This node in turn contains a number of subnodes
+  representing CPUs, which define properties for every cpu.
+
+  Bindings for CPU nodes follow the Devicetree Specification, available from:
+
+  https://www.devicetree.org/specifications/
+
+properties:
+  $nodename:
+    const: cpus
+    description:
+      A /cpus node is required for all Devicetrees.  It does not represent
+      a real device in the system, but acts as a container for child "cpu"
+      nodes which represent the systems' CPUs.
+
+  '#address-cells':
+    minimum: 1
+    description:
+      The value specifies how many cells each element of the reg property
+      array takes in children of this node.
+
+  '#size-cells':
+    const: 0
+
+patternProperties:
+  '^cpu@[0-9a-f]+$':
+    type: object
+    properties:
+      device_type:
+        const: cpu
+
+      reg:
+        oneOf:
+          - $ref: "/schemas/types.yaml#/definitions/uint32-array"
+        description:
+          Defines a unique CPU/thread ID for the CPU/threads represented
+          by the CPU node.
+
+      compatible: true
+
+      clock-frequency:
+        description:
+          Specifies the current clock speed of the CPU in Hertz.
+
+      timebase-frequency:
+        oneOf:
+          - $ref: "/schemas/types.yaml#/definitions/uint32"
+          - $ref: "/schemas/types.yaml#/definitions/uint64"
+        minimum: 1
+        description:
+          Specifies the current frequency at which the timebase and the
+          decrementer registers are updated (in Hertz).
+
+      enable-method:
+        $ref: "/schemas/types.yaml#/definitions/string-array"
+        description:
+          Describes the method by which a CPU in a disabled state is enabled.
+          This property is required for CPUs with a status property with a
+          value of "disabled".  The value consists of one or more strings
+          that define the method to release this CPU.  If a client program
+          recognizes any of the methods, it may use it.
+
+      cpu-release-addr:
+        $ref: "/schemas/types.yaml#/definitions/uint64"
+        description:
+          This value specifies the physical address of a spin table entry that
+          releases a secondary CPU from its spin loop.
+
+      cache-op-block-size:
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        description:
+          Specifies the block size in bytes upon which cache block instructions
+          operate.  Required if different than the L1 cache block size.
+
+      reservation-granule-size:
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        description:
+          Specifies the reservation granule size supported by this processor
+          in bytes.
+
+      mmu-type:
+        type: string
+        description:
+          Specifies the CPU's MMU type.
+
+      tlb-split:
+        $ref: "/schemas/types.yaml#/definitions/flag"
+        description:
+          If present, specifies that the TLB has a split configuration, with
+          separate TLBs for instructions and data.  If absent, specifies that
+          the TLB has a unified configuration.  Required for a CPU with a
+          TLB in a split configuration.
+
+    patternProperties:
+      "^(i-|d-|)tlb-(size|sets)$":
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 1
+
+    anyOf:
+      - required:
+          - device_type
+      - required:
+          - reg
+      - required:
+          - compatible
+
+    dependencies:
+      cpu-release-addr:
+        properties:
+          enable-method:
+            const: spin-table
+      cache-size: [ 'cache-unified' ]
+      cache-sets: [ 'cache-unified' ]
+      cache-block-size: [ 'cache-unified' ]
+      cache-line-size: [ 'cache-unified' ]
+      d-tlb-size: [ 'tlb-split' ]
+      d-tlb-sets: [ 'tlb-split' ]
+      i-tlb-size: [ 'tlb-split' ]
+      i-tlb-sets: [ 'tlb-split' ]
+
+required:
+  - '#address-cells'
+  - '#size-cells'
-- 
2.20.1




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