On 7/23/23 6:04 PM, Jose E. Marchesi wrote:
Hi Yonghong.
. sign extended load
. sign extended mov
. bswap
. signed div/mod
. ja with 32-bit offset
I am adding the V4 BPF instructions to binutils. Where is the precise
"pseudo-c" syntax used by the new instructions documented?
I looked at the tests in https://reviews.llvm.org/D144829 and:
For ALU sdiv/smod we are using:
rd s/= rs
rd s%= rs
Looks like I chose wisely, just by chance 8-)
For ALU movs instruction I just made up:
rd s= (i8) rs
rd s= (i16) rs
rd s= (i32) rs
Just changed that in binutils [1] to
rd = (s8) rs
rd = (s16) rs
rd = (s32) rs
For ALU32 movs I just made up:
wd s= (i8) ws
wd s= (i16) ws
wd s= (i32) ws
Just changed that in binutils [1] to
wd = (s8) ws
wd = (s16) ws
wd = (s32) ws
[1] https://sourceware.org/pipermail/binutils/2023-July/128544.html
And finally for byte swap instructions:
rd = bswap16 rd
rd = bswap32 rd
rd = bswap64 rd
https://sourceware.org/pipermail/binutils/2023-July/128546.html
So, at this point we should have support for all the new BPF V4
instructions in the binutils opcodes, assembler and disassembler.
We are working now in getting GCC making good use of them.
Sounds great. Thanks!
I plan to push cpu v4 to llvm18 which should be available in the
next week.
Salud!
