Re: [PATCH bpf-next v2 00/15] bpf: Support new insns from cpu v4

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> Hi Yonghong.
>
>>>>>    . sign extended load
>>>>>    . sign extended mov
>>>>>    . bswap
>>>>>    . signed div/mod
>>>>>    . ja with 32-bit offset
>
> I am adding the V4 BPF instructions to binutils.  Where is the precise
> "pseudo-c" syntax used by the new instructions documented?

I looked at the tests in https://reviews.llvm.org/D144829 and:

> For ALU sdiv/smod we are using:
>
>    rd s/= rs
>    rd s%= rs

Looks like I chose wisely, just by chance 8-)

> For ALU movs instruction I just made up:
>
>    rd s= (i8) rs
>    rd s= (i16) rs
>    rd s= (i32) rs

Just changed that in binutils [1] to

  rd = (s8) rs
  rd = (s16) rs
  rd = (s32) rs

> For ALU32 movs I just made up:
>
>    wd s= (i8) ws
>    wd s= (i16) ws
>    wd s= (i32) ws

Just changed that in binutils [1] to

  wd = (s8) ws
  wd = (s16) ws
  wd = (s32) ws

[1] https://sourceware.org/pipermail/binutils/2023-July/128544.html




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