> On Wed, Feb 12, 2025 at 09:55:43PM -0800, Alexei Starovoitov wrote:
> > How about:
> > #define BPF_LOAD_ACQ 2
> > #define BPF_STORE_REL 3
> >
> > and only use them with BPF_MOV like
> >
> > imm = BPF_MOV | BPF_LOAD_ACQ - is actual load acquire
> > imm = BPF_MOV | BPF_STORE_REL - release
Based on everything discussed, should we proceed with the above
suggestion? Specifically:
#define BPF_LD_ST BPF_MOV /* 0xb0 */
#define BPF_LOAD_ACQ 0x2
#define BPF_STORE_REL 0x3
(And document that BPF_LD_ST cannot be used together with BPF_FETCH.)
So that:
1. We avoid "aliasing" with BPF_SUB or BPF_MUL at all.
2. If we need to add cmpwait_relaxed, we can then expand imm<4-7> to
e.g. imm<4-11> and do something similar to:
XCHG 0x0e0 | FETCH
CMPXCHG 0x0f0 | FETCH
+CMPWAIT_RELAXED 0x100
So that <asm/cmpxchg.h> operations can "stay together".
3. In the hypothetical scenario where we need seq_cst loads/stores, we
add new flags to imm<0-3>.
Though considering that:
* BPF_FETCH doesn't apply to loads/stores, and
* BPF_LOAD_ACQ and BPF_STORE_REL don't apply to RMW operatons
* We only have 15 numbers for imm<0-3> flags
I do think it makes sense to define BPF_LOAD_ACQ and BPF_STORE_REL as 1
and 2 (instead of 2 and 3). With proper documentation I believe it'll
be clear that load/store and RMW are separate categories, with different
ways of using imm<0-3> (or, different imm<0-3> "namespace"s). That
said, I'm happy to do either 2 and 3, or 1 and 2.
I'll start making changes for v3 and the LLVM PR, according to the
description above (with BPF_LOAD_ACQ=2, BPF_STORE_REL=3). Please advise
me of any further concerns.
Thanks,
Peilin Ye
