On Mon, Feb 10, 2025 at 10:51:11PM +0000, Peilin Ye wrote: > > > #define BPF_LOAD_ACQ 0x10 > > > #define BPF_STORE_REL 0x20 > > > > why not 1 and 2 ? > > I just realized that we can't do 1 and 2 because BPF_ADD | BPF_FETCH > also equals 1. > > > All other bits are reserved and the verifier will make sure they're zero > > IOW, we can't tell if imm<4-7> is reserved or BPF_ADD (0x00). What > would you suggest? Maybe: > > #define BPF_ATOMIC_LD_ST 0x10 > > #define BPF_LOAD_ACQ 0x1 > #define BPF_STORE_REL 0x2 > > ? Or, how about reusing 0xb in imm<4-7>: #define BPF_ATOMIC_LD_ST 0xb0 #define BPF_LOAD_ACQ 0x1 #define BPF_STORE_REL 0x2 0xb is BPF_MOV in BPFArithOp<>, and we'll never need it for BPF_ATOMIC. Instead of moving values between registers, we now "move" values from/to the memory - if I can think of it that way. - - - Or, do we want to start to use the remaining bits of the imm field (i.e. imm<8-31>) ? Thanks, Peilin Ye
