Hi Alexei, On Sat, Feb 08, 2025 at 07:46:54PM -0800, Alexei Starovoitov wrote: > > Got it! In v3, I'll change it back to: > > > > #define BPF_LOAD_ACQ 0x10 > > #define BPF_STORE_REL 0x20 > > why not 1 and 2 ? I just realized that we can't do 1 and 2 because BPF_ADD | BPF_FETCH also equals 1. > All other bits are reserved and the verifier will make sure they're zero IOW, we can't tell if imm<4-7> is reserved or BPF_ADD (0x00). What would you suggest? Maybe: #define BPF_ATOMIC_LD_ST 0x10 #define BPF_LOAD_ACQ 0x1 #define BPF_STORE_REL 0x2 ? > , so when/if we need to extend it then it wouldn't matter whether > lower 4 bits are reserved or other bits. > Say, we decide to support cmpwait_relaxed as a new insn. > It can take the value 3 and arm64 JIT will map it to ldxr+wfe+... > > Then with this new load_acq and cmpwait_relaxed we can efficiently > implement both smp_cond_load_relaxed and smp_cond_load_acquire. Thanks, Peilin Ye
