On Sat, Feb 08, 2025 at 07:46:54PM -0800, Alexei Starovoitov wrote: > > > These values might imply that bpf infra is supposed to map all the values > > > to cpu instructions, but that's not what we're doing here. > > > We're only dealing with two specific instructions. > > > We're not defining a memory model for all future new instructions. > > > > Got it! In v3, I'll change it back to: > > > > #define BPF_LOAD_ACQ 0x10 > > #define BPF_STORE_REL 0x20 > > why not 1 and 2 ? > All other bits are reserved and the verifier will make sure they're zero, > so when/if we need to extend it then it wouldn't matter whether > lower 4 bits are reserved or other bits. > Say, we decide to support cmpwait_relaxed as a new insn. > It can take the value 3 and arm64 JIT will map it to ldxr+wfe+... > > Then with this new load_acq and cmpwait_relaxed we can efficiently > implement both smp_cond_load_relaxed and smp_cond_load_acquire. Ah, I see. When you suggested "LOAD_ACQ=1 and STORE_REL=2" earlier, I didn't realize you meant 1 and 2 in imm<0-3>. Thanks, Peilin Ye