On Thu, Feb 29, 2024 at 5:33 PM John Fastabend <john.fastabend@xxxxxxxxx> wrote: > > Singhai, Anjali wrote: > > From: Paolo Abeni <pabeni@xxxxxxxxxx> > > > > > I think/fear that this series has a "quorum" problem: different voices raises opposition, and nobody (?) outside the authors > > > supported the code and the feature. > > > > > Could be the missing of H/W offload support in the current form the root cause for such lack support? Or there are parties > > > interested that have been quite so far? > > > > Hi, > > Intel/AMD definitely need the p4tc offload support and a kernel SW pipeline, as a lot of customers using programmable pipeline (smart switch and smart NIC) prefer kernel standard APIs and interfaces (netlink and tc ndo). Intel and other vendors have native P4 capable HW and are invested in P4 as a dataplane specification. > > Great what hardware/driver and how do we get that code here so we can see > it working? Is the hardware available e.g. can I get ahold of one? > > What is programmable on your devices? Is this 'just' the parser graph or > are you slicing up tables and so on. Is it a FPGA, DPU architecture or a > TCAM architecture? How do you reprogram the device? I somehow doubt its > through a piecemeal ndo. But let me know if I'm wrong maybe my internal > architecture details are dated. Fully speculating the interface is a FW > big thunk to the device? > > Without any details its difficult to get community feedback on how the > hw programmable interface should work. The only reason I've even > bothered with this thread is I want to see P4 working. > > Who owns the AMD side or some other vendor so we can get something that > works across at least two vendors which is our usual bar for adding hw > offload things. > > Note if you just want a kernel SW pipeline we already have that so > I'm not seeing that as paticularly motivating. Again my point of view. > P4 as a dataplane specification is great but I don't see the connection > to this patchset without real hardware in a driver. Here's what you can buy on the market that are native P4 (not that it hasnt been mentioned from day 1 on patch 0 references): [10]https://www.intel.com/content/www/us/en/products/details/network-io/ipu/e2000-asic.html [11]https://www.amd.com/en/accelerators/pensando I want to emphasize again these patches are about the P4 s/w pipeline that is intended to work seamlessly with hw offload. If you are interested in h/w offload and want to contribute just show up at the meetings - they are open to all. The current offloadable piece is the match-action tables. The P4 specs may change to include parsers in the future or other objects etc (but not sure why we should discuss this in the thread). cheers, jamal
