On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> Change-Id: I54bb964a3905f675e93411f93810cc1aa1f67d12
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 ++
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 21 +++++++++++++++++++++
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 401b895..fba44a5 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -107,6 +107,8 @@ enum pp_clock_type {
> PP_SCLK,
> PP_MCLK,
> PP_PCIE,
> + OD_SCLK,
> + OD_MCLK,
> };
>
> enum amd_pp_sensors {
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index f3d9c64..a0007a8 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4355,6 +4355,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
> struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
> struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
> struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
> + struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
> + struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
> + struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
> int i, now, size = 0;
> uint32_t clock, pcie_speed;
>
> @@ -4409,6 +4412,24 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
> (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
> (i == now) ? "*" : "");
> break;
> + case OD_SCLK:
> + if (hwmgr->od_enabled) {
> + size = sprintf(buf, "%s: \n", "OD_SCLK");
> + for (i = 0; i < odn_sclk_table->num_of_pl; i++)
> + size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
> + i, odn_sclk_table->entries[i].clock / 100,
> + odn_sclk_table->entries[i].vddc);
> + }
> + break;
> + case OD_MCLK:
> + if (hwmgr->od_enabled) {
> + size = sprintf(buf, "%s: \n", "OD_MCLK");
> + for (i = 0; i < odn_mclk_table->num_of_pl; i++)
> + size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
> + i, odn_mclk_table->entries[i].clock / 100,
> + odn_mclk_table->entries[i].vddc);
> + }
> + break;
> default:
> break;
> }
> --
> 1.9.1
>
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