On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> when this bit was set on module load,
> driver will allow the user over/under gpu
> clock and voltage through sysfs.
>
> by default, this bit was not set.
>
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 3 +++
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 ++----
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 ++-----
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++
> 5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index e679bb8..508a254 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -120,7 +120,7 @@
> uint amdgpu_sdma_phase_quantum = 32;
> char *amdgpu_disable_cu = NULL;
> char *amdgpu_virtual_display = NULL;
> -uint amdgpu_pp_feature_mask = 0xffffffff;
> +uint amdgpu_pp_feature_mask = 0x2fff;
Setting the feature mask to 0x2fff unsets PP_SOCCLK_DPM_MASK.
Probably not intended. I think you want 0x3fff.
Alex
> int amdgpu_ngg = 0;
> int amdgpu_prim_buf_per_se = 0;
> int amdgpu_pos_buf_per_se = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index e35bdc5..ebfbbcf 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
> PHM_PlatformCaps_CAC);
> }
>
> + if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)
> + hwmgr->od_enabled = true;
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 6f053fa..ce74e06 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3572,8 +3572,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->sclk_table.dpm_levels
> [dpm_table->sclk_table.count - 1].value = sclk;
>
> - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
> - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
> + if (hwmgr->od_enabled) {
> /* Need to do calculation based on the golden DPM table
> * as the Heatmap GPU Clock axis is also based on the default values
> */
> @@ -3618,8 +3617,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->mclk_table.dpm_levels
> [dpm_table->mclk_table.count - 1].value = mclk;
>
> - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
> - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
> + if (hwmgr->od_enabled) {
>
> PP_ASSERT_WITH_CODE(
> (golden_dpm_table->mclk_table.dpm_levels
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index fadbc8a..12a31d1 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -3396,8 +3396,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->
> gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
> value = sclk;
> - if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
> - PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
> + if (hwmgr->od_enabled) {
> /* Need to do calculation based on the golden DPM table
> * as the Heatmap GPU Clock axis is also based on
> * the default values
> @@ -3451,9 +3450,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
> mem_table.dpm_levels[dpm_table->mem_table.count - 1].
> value = mclk;
>
> - if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
> - PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
> -
> + if (hwmgr->od_enabled) {
> PP_ASSERT_WITH_CODE(
> golden_dpm_table->mem_table.dpm_levels
> [golden_dpm_table->mem_table.count - 1].value,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 6d8183d..c496742 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -84,6 +84,7 @@ enum PP_FEATURE_MASK {
> PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
> PP_SOCCLK_DPM_MASK = 0x1000,
> PP_DCEFCLK_DPM_MASK = 0x2000,
> + PP_OVER_DRIVER_MASK = 0x4000,
> };
>
> enum PHM_BackEnd_Magic {
> @@ -755,6 +756,7 @@ struct pp_hwmgr {
> uint32_t power_profile_mode;
> uint32_t pstate_sclk;
> uint32_t pstate_mclk;
> + bool od_enabled;
> };
>
> struct cgs_irq_src_funcs {
> --
> 1.9.1
>
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