This DC patchset brings improvements in multiple areas. In summary, we
have:
* Expand dmub_cmd operations.
* Update DVI configuration.
* Modify power sequence.
* Enable Z10 flag for IPS.
* Multiple code cleanups.
Cc: Daniel Wheeler <daniel.wheeler@xxxxxxx>
Thanks
Siqueira
Anthony Koo (1):
drm/amd/display: Expand dmub_cmd operations
Aric Cyr (1):
drm/amd/display: 3.2.281
Bitnun, Ethan (1):
drm/amd/display: Improve the log precision
Chaitanya Dhere (1):
drm/amd/display: Fix incorrect pointer assignment
Charlene Liu (1):
drm/amd/display: limit the code change to ips enabled asic
Chris Park (1):
drm/amd/display: Add a function for checking tmds mode
Eric Bernstein (1):
drm/amd/display: Update FMT settings for 4:2:0
Mikita Lipski (1):
drm/amd/display: Fix PSR command version passed
Nicholas Kazlauskas (1):
drm/amd/display: Pass sequential ONO bit to DMCUB boot options
Rodrigo Siqueira (11):
drm/amd/display: Use dce_version instead of chip_id
drm/amd/display: Adjust headers
drm/amd/display: Group scl_data together in
resource_build_scaling_params
drm/amd/display: Replace int with unsigned int
drm/amd/display: Update some comments to improve the code readability
drm/amd/display: Remove unnecessary code
drm/amd/display: Rework dcn10_stream_encoder header
drm/amd/display: Move REG sequence from program ogam to idle before
connect
drm/amd/display: Update DCN201 link encoder registers
drm/amd/display: Add missing callback for init_watermarks in DCN 301
drm/amd/display: Add missing replay field
Samson Tam (1):
drm/amd/display: add support for chroma offset
Sung Joon Kim (4):
drm/amd/display: Modify power sequence
drm/amd/display: Modify resource allocation logic
drm/amd/display: Enable Z10 flag for IPS FSM
drm/amd/display: Rework power sequence and resource allocation logic
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 +-
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 3 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 5 +-
.../gpu/drm/amd/display/dc/core/dc_state.c | 10 +-
.../gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc.h | 16 +-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 +
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 6 -
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 6 -
.../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 9 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 2 +
.../display/dc/dcn10/dcn10_stream_encoder.h | 10 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 2 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 10 +-
.../drm/amd/display/dc/dcn201/dcn201_hubp.c | 5 +
.../display/dc/dcn201/dcn201_link_encoder.h | 14 +-
.../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 18 --
.../dc/dcn30/dcn30_dio_stream_encoder.c | 1 -
.../gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c | 2 -
.../drm/amd/display/dc/dcn301/dcn301_hubbub.c | 1 +
drivers/gpu/drm/amd/display/dc/hwss/Makefile | 2 +-
.../drm/amd/display/dc/hwss/dcn351/Makefile | 25 ++-
.../amd/display/dc/hwss/dcn351/dcn351_hwseq.c | 182 ++++++++++++++++++
.../amd/display/dc/hwss/dcn351/dcn351_hwseq.h | 41 ++++
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 1 +
.../dc/resource/dcn32/dcn32_resource.c | 4 +-
.../dc/resource/dcn32/dcn32_resource.h | 6 +
.../dc/resource/dcn351/dcn351_resource.c | 5 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 53 ++++-
.../gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 1 +
.../drm/amd/display/include/signal_types.h | 13 ++
35 files changed, 402 insertions(+), 82 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h
--
2.43.0
