[Public]
Hi all,
This week this patchset was tested on the following systems:
* Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U
* MSI Gaming X Trio RX 6800
* Gigabyte Gaming OC RX 7900 XTX
These systems were tested on the following display/connection types:
* eDP, (1080p 60hz [5650U]) (1920x1200 60hz [6600U]) (2560x1600 120hz[6600U])
* VGA and DVI (1680x1050 60hz [DP to VGA/DVI, USB-C to VGA/DVI])
* DP/HDMI/USB-C (1440p 170hz, 4k 60hz, 4k 144hz, 4k 240hz [Includes USB-C to DP/HDMI adapters])
* Thunderbolt (LG Ultrafine 5k)
* MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60Hz displays)
* DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60 displays, and HP Hook G2 with 1 4k60 display)
* USB 4 (Kensington SD5700T and 1x 4k 60Hz display)
* PCON (Club3D CAC-1085 and 1x 4k 144Hz display [at 4k 120HZ, as that is the max the adapter supports])
The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to):
* Changing display configurations and settings
* Benchmark testing
* Feature testing (Freesync, etc.)
Automated testing includes (but is not limited to):
* Script testing (scripts to automate some of the manual checks)
* IGT testing
The patchset consists of the amd-staging-drm-next branch (Head commit - 9ef923c9f876 drm/amd/display: 3.2.280) with new patches added on top of it.
Tested on Ubuntu 22.04.3, on Wayland and X11, using KDE Plasma and Gnome.
Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
Thank you,
Dan Wheeler
Sr. Technologist | AMD
SW Display
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1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
amd.com
-----Original Message-----
From: Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>
Sent: Wednesday, April 10, 2024 5:26 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Wentland, Harry <Harry.Wentland@xxxxxxx>; Li, Sun peng (Leo) <Sunpeng.Li@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>; Pillai, Aurabindo <Aurabindo.Pillai@xxxxxxx>; Li, Roman <Roman.Li@xxxxxxx>; Lin, Wayne <Wayne.Lin@xxxxxxx>; Gutierrez, Agustin <Agustin.Gutierrez@xxxxxxx>; Chung, ChiaHsuan (Tom) <ChiaHsuan.Chung@xxxxxxx>; Wu, Hersen <hersenxs.wu@xxxxxxx>; Zuo, Jerry <Jerry.Zuo@xxxxxxx>; Wheeler, Daniel <Daniel.Wheeler@xxxxxxx>
Subject: [PATCH 00/25] DC Patches April 10, 2024
This DC patchset brings improvements in multiple areas. In summary, we
have:
* Expand dmub_cmd operations.
* Update DVI configuration.
* Modify power sequence.
* Enable Z10 flag for IPS.
* Multiple code cleanups.
Cc: Daniel Wheeler <daniel.wheeler@xxxxxxx>
Thanks
Siqueira
Anthony Koo (1):
drm/amd/display: Expand dmub_cmd operations
Aric Cyr (1):
drm/amd/display: 3.2.281
Bitnun, Ethan (1):
drm/amd/display: Improve the log precision
Chaitanya Dhere (1):
drm/amd/display: Fix incorrect pointer assignment
Charlene Liu (1):
drm/amd/display: limit the code change to ips enabled asic
Chris Park (1):
drm/amd/display: Add a function for checking tmds mode
Eric Bernstein (1):
drm/amd/display: Update FMT settings for 4:2:0
Mikita Lipski (1):
drm/amd/display: Fix PSR command version passed
Nicholas Kazlauskas (1):
drm/amd/display: Pass sequential ONO bit to DMCUB boot options
Rodrigo Siqueira (11):
drm/amd/display: Use dce_version instead of chip_id
drm/amd/display: Adjust headers
drm/amd/display: Group scl_data together in
resource_build_scaling_params
drm/amd/display: Replace int with unsigned int
drm/amd/display: Update some comments to improve the code readability
drm/amd/display: Remove unnecessary code
drm/amd/display: Rework dcn10_stream_encoder header
drm/amd/display: Move REG sequence from program ogam to idle before
connect
drm/amd/display: Update DCN201 link encoder registers
drm/amd/display: Add missing callback for init_watermarks in DCN 301
drm/amd/display: Add missing replay field
Samson Tam (1):
drm/amd/display: add support for chroma offset
Sung Joon Kim (4):
drm/amd/display: Modify power sequence
drm/amd/display: Modify resource allocation logic
drm/amd/display: Enable Z10 flag for IPS FSM
drm/amd/display: Rework power sequence and resource allocation logic
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 +-
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 3 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 5 +-
.../gpu/drm/amd/display/dc/core/dc_state.c | 10 +-
.../gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc.h | 16 +-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 +
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 6 -
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 6 -
.../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 9 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 2 +
.../display/dc/dcn10/dcn10_stream_encoder.h | 10 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 2 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 10 +-
.../drm/amd/display/dc/dcn201/dcn201_hubp.c | 5 +
.../display/dc/dcn201/dcn201_link_encoder.h | 14 +-
.../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 18 --
.../dc/dcn30/dcn30_dio_stream_encoder.c | 1 -
.../gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c | 2 -
.../drm/amd/display/dc/dcn301/dcn301_hubbub.c | 1 +
drivers/gpu/drm/amd/display/dc/hwss/Makefile | 2 +-
.../drm/amd/display/dc/hwss/dcn351/Makefile | 25 ++-
.../amd/display/dc/hwss/dcn351/dcn351_hwseq.c | 182 ++++++++++++++++++ .../amd/display/dc/hwss/dcn351/dcn351_hwseq.h | 41 ++++
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 1 +
.../dc/resource/dcn32/dcn32_resource.c | 4 +-
.../dc/resource/dcn32/dcn32_resource.h | 6 +
.../dc/resource/dcn351/dcn351_resource.c | 5 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 53 ++++-
.../gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 1 +
.../drm/amd/display/include/signal_types.h | 13 ++
35 files changed, 402 insertions(+), 82 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h
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2.43.0
