On Wed, Oct 28, 2015 at 09:11:39AM +0100, Roberto Fichera wrote: > I'm also having the same issue but employing SSI in TDM master mode against a SLIC Si32178 > using its PCM mode. PCLK is at 2048KHz, FSYNC is 8KHz slot length is 32 bits (SSI wants > this since when in master mode) but valid data set to be 8bits in the SSI register. > My Current situation is that I've a custom fsl_ssi.c driver to control the SSI in TDM master mode > both PCLK and FSYNC works perfectly fine, the SLIC has a register that I can check via SPI for > such purpose, I can see the clocking status from its side. The main problem I've is exactly the same > Caleb is having, after a certain amount of SDMA transfers, roughly 1000 or so, everything stops > without any apparent reason. I will start to help you to figure out your problem. But it seems that you are having a different issue here with clock generation. I don't get why you said *same issue*. For double confirm, the the "everything stops" mentioned, does it mean that clock from SSI stops? _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
