On Wed, Oct 28, 2015 at 09:23:01AM +0100, Roberto Fichera wrote: > On 10/27/2015 09:11 PM, Nicolin Chen wrote: > > On Tue, Oct 27, 2015 at 08:13:44AM +0100, Markus Pargmann wrote: > > > >>> So, the dma priority doesn't seem to be the issue. It's now set in > >>> the device tree, and strangely it's set to priority 0 (the highest) > >>> along with the UARTS. priority 0 is just the highest in the device > >>> tree -- it gets remapped to priority 3 in the sdma driver. the DT > >>> exposes only 3 levels of DMA priority, low, medium, and high. I > >>> created a new level that maps to DMA priroity 7 (the highest in the > >>> hardware), but still got the problem. > >>> > >>> So, still something unknown causing dma to miss samples. must be in > >>> the dma ISR I would assume. I guess it's time to look into that. > >> Cc Nicolin, Fabio, Shawn > >> > >> Perhaps you have an idea about this? > > Off the top of my head: > > > > 1) Enable TUE0, TUE1, ROE0, ROE1 to see if there is any IRQ trigged. > > I'm my case I was never able to see an interrupt triggered when setting both RDMAE and TDMAE > bits in the SIER register. Your problem may not involve with hardware FIFO underrun at all so it's quite normal for you to have no IRQ in my opinion. _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
