Am Donnerstag, 14. Oktober 2010, 13:16:12 schrieb Daniel Mack: > > Sure, attached you see a capture while running speaker-test to generate a > > 1khz sine wave on one channel. (Blue: BCLK 1,536MHz, Yellow: LRCLK: > > 48kHz, Green: I2S data) > > If you want to see more/other captures just let me know what you need. > > The dump doesn't show whether the LRCLK is symmetrical, iow, whether the > low phase of LRCLK has the same number of BCLK cycles as the high phase. > > But if that's the case, the signals do indeed look alright. Maybe you > need the configure the codec to this format? Hi, I did a capture of the same signal, but this time not just a short snap, but a whole memory dump of the oscilloscope. I did a plot with gnuplot and uploaded it here: http://jusst.de/files/i2s_plot.png As it's 0,5MB big I didn't want to send it as attachment... Would you agree that the data (this time blue channel) is delayed too much? Looks like it's at least 2 cycles behind the LRCK toggle. Would it be possible that this is the reason for the DAC not understanding the data? Regards, Julian _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
