> Would you agree that the data (this time blue channel) is delayed too much? > Looks like it's at least 2 cycles behind the LRCK toggle. > Would it be possible that this is the reason for the DAC not understanding the > data? > Yes it is delayed 2-3 cycles (should be only 1 cycle). Also, as I pointed out earlier, data is valid on falling edge of clock. Should be rising edge according to i2S. Alex _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
