Hi, > Based on the inputs/suggestions from Tudor, i am planning to add a new > layer between the SPI-NOR and MTD layers to support stacked and parallel > configurations. This new layer will be part of the spi-nor and located in > mtd/spi-nor/ Will AMD submit to maintain this layer? What happens if the maintainer will leave AMD? TBH, personally, I don't like to maintain such a niche feature. I'd really like to see some use cases and performance reports for this, like actual boards (and no evaluation boards don't count). Why wouldn't someone just use an octal flash? And as already mentioned there is also mtdcat, which seems to duplicate some features? -michael
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