At Fri, 16 Mar 2007 12:54:02 +0100,
Joachim Deguara wrote:
>
> >From the HDA spec it appears that the buffers written to the BDL and
> sent to a codec must be 128 byte aligned (section 4.5.1). The alignment
> was not happening especially when playing 6 channels. This patch set
> the alignment of buffers and periods to 128 bytes.
Good catch.
The changes look good to me, but please fold lines to fit within 80
chars. Also, please give a sign-off for the patch to apply to the
upstream.
Thanks,
Takashi
> -Joachim
> [2 align_hda_buffers <text/plain (base64)>]
> diff -r f8284261b2be pci/hda/hda_intel.c
> --- a/pci/hda/hda_intel.c Thu Mar 15 15:10:28 2007 +0100
> +++ b/pci/hda/hda_intel.c Fri Mar 16 06:34:03 2007 +0100
> @@ -1087,6 +1087,10 @@ static int azx_pcm_open(struct snd_pcm_s
> runtime->hw.rates = hinfo->rates;
> snd_pcm_limit_hw_rates(runtime);
> snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
> + snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
> +128);
> + snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
> +128);
> if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
> azx_release_device(azx_dev);
> mutex_unlock(&chip->open_mutex);
> [3 <text/plain; us-ascii (7bit)>]
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