Re: Mapping GPIO Pins from Wandboard to Fedora/libpiod

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Hi,

First, thank you for all the time you're putting into helping me.
I really do appreciate it, especially since the platform is not currently
supported.

(More below)

On Mon, April 15, 2024 4:49 pm, Peter Robinson wrote:
> On Mon, 15 Apr 2024 at 21:38, Derek Atkins <derek@xxxxxxxxx> wrote:
>>
>> Hi,
>>
>> On Mon, April 15, 2024 4:21 pm, Peter Robinson wrote:
>>
>> >> >> >> me that the JP4 header connects to GPIO3_12, GPIO3_27,
>> GPIO6_31,
>> >> >> >> CPIO1_24,
>> >> >> >> GPIO7_8, GPIO3_26, GPIO_18, and GPIO_19.
>> >> >> >>
>> >> [snip]
>>
>> > I've not dug out a pdf to work out the physical pins and how they map
>> > to the SOC and hence the DT, I've left that up to you, I was just
>> > answering your questions about why some appear to be in use and trying
>> > to help you understand as you requested.

By "docs", I am looking at the schematics.  Starting at JP4, we have:

JP4 4 -> GPIO3_12 -> MXM Pin 256 -> EIM_DA11 -> IMX6 NVCC_EIM2 EIM_DA11 (M20)
JP4 6 -> GPIO3_27 -> MXM Pin 258 -> GPIO3_27 -> IMX6 NVCC_EIM0 EIM_D27 (E25)
JP4 8 -> GPIO6_31 -> MXM Pin 260 -> GPIO6_31 -> IMX6 NVCC_EIM2 EIM_BCLK (N22)
JP4 10-> GPIO1_24 -> MXM Pin 262 -> MIC_DET  -> IMX6 NVCC_ENET ENET_RX_ER
(W23)
JP4 12-> GPIO7_8  -> MXM Pin 264 -> SD3_RST  -> IMX6 NVCC_SD3 SD3_RST (D15)
JP4 14-> GPIO3_26 -> MXM Pin 259 -> GPIO3_26 -> IMX6 NVCC_EIM0 EIM_D26 (E24)
JP4 16-> GPIO_18  -> MXM Pin 261 -> EIM_DA8  -> IMX6 NVCC_EIM2 EIM_DA8 (L24)
JP4 18-> GPIO_19  -> MXM Pin 263 -> GPIO_19  -> IMX6 NVCC_GPIO GPIO_19 (P5)

So clearly some of the JP4 pins get "renamed" when crossing the MXM
connector boundary, and some get renamed again when connecting to the
IMX6.  However, I still don't know how to map the e.g. IMX6 NVCC_GPIO to a
libgpiod gpiochipN.

> In both cases above it should be in the docs, or at the very least the
> DT in combination with the docs. In the later case they should
> document what GPIOs are available for use and what the pins on the
> header do similar to how the RPi document the 40 pin header there.

One would expect that, but I'm having a heck of a time tracking that down.

-derek

-- 
       Derek Atkins                 617-623-3745
       derek@xxxxxxxxx             www.ihtfp.com
       Computer and Internet Security Consultant
--
_______________________________________________
arm mailing list -- arm@xxxxxxxxxxxxxxxxxxxxxxx
To unsubscribe send an email to arm-leave@xxxxxxxxxxxxxxxxxxxxxxx
Fedora Code of Conduct: https://docs.fedoraproject.org/en-US/project/code-of-conduct/
List Guidelines: https://fedoraproject.org/wiki/Mailing_list_guidelines
List Archives: https://lists.fedoraproject.org/archives/list/arm@xxxxxxxxxxxxxxxxxxxxxxx
Do not reply to spam, report it: https://pagure.io/fedora-infrastructure/new_issue




[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Index of Archives]     [Linux ARM (Vger)]     [Linux ARM]     [ARM Kernel]     [Fedora User Discussion]     [Older Fedora Users Discussion]     [Fedora Advisory Board]     [Fedora Security]     [Fedora Maintainers]     [Fedora Devel Java]     [Fedora Legacy]     [Fedora Desktop]     [ATA RAID]     [Fedora Marketing]     [Fedora Mentors]     [Fedora Package Announce]     [Fedora Package Review]     [Fedora Music]     [Fedora Packaging]     [Centos]     [Fedora SELinux]     [Coolkey]     [Yum Users]     [Tux]     [Yosemite News]     [Linux Apps]     [KDE Users]     [Fedora Tools]     [Fedora Art]     [Fedora Docs]     [Asterisk PBX]

Powered by Linux