On Mon, 15 Apr 2024 at 21:38, Derek Atkins <derek@xxxxxxxxx> wrote: > > Hi, > > On Mon, April 15, 2024 4:21 pm, Peter Robinson wrote: > > >> >> >> me that the JP4 header connects to GPIO3_12, GPIO3_27, GPIO6_31, > >> >> >> CPIO1_24, > >> >> >> GPIO7_8, GPIO3_26, GPIO_18, and GPIO_19. > >> >> >> > >> [snip] > > > I've not dug out a pdf to work out the physical pins and how they map > > to the SOC and hence the DT, I've left that up to you, I was just > > answering your questions about why some appear to be in use and trying > > to help you understand as you requested. > > I've read the docs; the pins on the header map to the above-listed lanes. > What I need to figure out are: > > 1) How do these map to gpiochipN X -- e.g. if GPIO_18 maps to gpiochip0,18 > and GPIO3_12 maps to gpiochip3,12 -- what does GPIO7_8 map to? > > 2) How to figure out which ones are available? I presume I can just look > at the output of gpioinfo for the aforementioned mappings? In both cases above it should be in the docs, or at the very least the DT in combination with the docs. In the later case they should document what GPIOs are available for use and what the pins on the header do similar to how the RPi document the 40 pin header there. -- _______________________________________________ arm mailing list -- arm@xxxxxxxxxxxxxxxxxxxxxxx To unsubscribe send an email to arm-leave@xxxxxxxxxxxxxxxxxxxxxxx Fedora Code of Conduct: https://docs.fedoraproject.org/en-US/project/code-of-conduct/ List Guidelines: https://fedoraproject.org/wiki/Mailing_list_guidelines List Archives: https://lists.fedoraproject.org/archives/list/arm@xxxxxxxxxxxxxxxxxxxxxxx Do not reply to spam, report it: https://pagure.io/fedora-infrastructure/new_issue
