Hi,
On Mon, April 15, 2024 4:21 pm, Peter Robinson wrote:
>> >> >> me that the JP4 header connects to GPIO3_12, GPIO3_27, GPIO6_31,
>> >> >> CPIO1_24,
>> >> >> GPIO7_8, GPIO3_26, GPIO_18, and GPIO_19.
>> >> >>
>> [snip]
> I've not dug out a pdf to work out the physical pins and how they map
> to the SOC and hence the DT, I've left that up to you, I was just
> answering your questions about why some appear to be in use and trying
> to help you understand as you requested.
I've read the docs; the pins on the header map to the above-listed lanes.
What I need to figure out are:
1) How do these map to gpiochipN X -- e.g. if GPIO_18 maps to gpiochip0,18
and GPIO3_12 maps to gpiochip3,12 -- what does GPIO7_8 map to?
2) How to figure out which ones are available? I presume I can just look
at the output of gpioinfo for the aforementioned mappings?
Thanks,
-derek
--
Derek Atkins 617-623-3745
derek@xxxxxxxxx www.ihtfp.com
Computer and Internet Security Consultant
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