Hi, Have you patched your 3c59x module to support 802.1q ? If not i add the patch in attachment, it work properly for me with 2.4.27 vanilla kernel under slackware 9.1 A++ Magnus Ternstr?m wrote: > Hi, > > I have a problem with getting vlan to work on my linux comp with a 3com > 905C. > > Adding the vlans with vconfig isn't a problem. > I've set up eth1.1 - 5 and addressed them with separate 192.168.* > networks. > The Cisco 3500XL is configured for trunking with dot1q on fa0/1. > > The problem is that when i look at the traffic in iptraf and ping the > router from the switch > the ICMP packets come in on eth1, not eth1.1. > Same thing when setting port 0/2 on the switch to vlan 2 and connecting > a computer to it. > DHCP requests incoming on the unaddressed eth1 interface. > > it was a few years ago i got my CCNP so i dont remember how to check > trunk negotiation. > Show interfaces fa 0/1 dont give me any clues to if the trunk works or > not. > > Thanks in advance, > Magnus Ternstr?m > > > > ------------------------------------------------------------------------ > > _______________________________________________ > Vlan mailing list > Vlan@xxxxxxxxxxxx > http://www.lanforge.com/mailman/listinfo/vlan -- ---------------------------------------------- COLIN Stephane, scolin [at] planetepc [dot] fr ---------------------------------------------- -------------- next part -------------- --- ./drivers/net/3c59x.c 2003-11-28 19:26:20.000000000 +0100 +++ /usr/src/linux-2.4.25/drivers/net/3c59x.c 2004-04-06 12:07:29.000000000 +0200 @@ -313,6 +313,9 @@ code size of a per-interface flag is not worthwhile. */ static char mii_preamble_required; +/* The Ethernet Type used for 802.1q tagged frames */ +#define VLAN_ETHER_TYPE 0x8100 + #define PFX DRV_NAME ": " @@ -681,7 +684,7 @@ Wn2_ResetOptions=12, }; enum Window3 { /* Window 3: MAC/config bits. */ - Wn3_Config=0, Wn3_MAC_Ctrl=6, Wn3_Options=8, + Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8, }; #define BFEXT(value, offset, bitcount) \ @@ -709,7 +712,8 @@ Media_LnkBeat = 0x0800, }; enum Window7 { /* Window 7: Bus Master control. */ - Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12, + Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6, + Wn7_MasterStatus = 12, }; /* Boomerang bus master control registers. */ enum MasterCtrl { @@ -806,7 +810,8 @@ pm_state_valid:1, /* power_state[] has sane contents */ open:1, medialock:1, - must_free_region:1; /* Flag: if zero, Cardbus owns the I/O region */ + must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */ + large_frames:1; /* accept large frames */ int drv_flags; u16 status_enable; u16 intr_enable; @@ -874,6 +879,9 @@ static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); static void vortex_tx_timeout(struct net_device *dev); static void acpi_set_WOL(struct net_device *dev); +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) +static void set_8021q_mode(struct net_device *dev, int enable); +#endif static struct ethtool_ops vortex_ethtool_ops; /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */ @@ -1058,6 +1066,7 @@ dev->base_addr = ioaddr; dev->irq = irq; dev->mtu = mtu; + vp->large_frames = mtu > 1500; vp->drv_flags = vci->drv_flags; vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0; vp->io_size = vci->io_size; @@ -1482,7 +1491,7 @@ /* Set the full-duplex bit. */ outw( ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) | - (dev->mtu > 1500 ? 0x40 : 0) | + (vp->large_frames ? 0x40 : 0) | ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0), ioaddr + Wn3_MAC_Ctrl); @@ -1566,6 +1575,10 @@ } /* Set receiver mode: presumably accept b-case and phys addr only. */ set_rx_mode(dev); +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) + /* enable 802.1q tagged frames */ + set_8021q_mode(dev, 1); +#endif outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */ // issue_and_wait(dev, SetTxStart|0x07ff); @@ -1706,7 +1719,7 @@ /* Set the full-duplex bit. */ EL3WINDOW(3); outw( (vp->full_duplex ? 0x20 : 0) | - (dev->mtu > 1500 ? 0x40 : 0) | + (vp->large_frames ? 0x40 : 0) | ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0), ioaddr + Wn3_MAC_Ctrl); if (vortex_debug > 1) @@ -1929,6 +1942,10 @@ issue_and_wait(dev, RxReset|0x07); /* Set the Rx filter to the current state. */ set_rx_mode(dev); +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) + /* enable 802.1q VLAN tagged frames */ + set_8021q_mode(dev, 1); +#endif outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */ outw(AckIntr | HostError, ioaddr + EL3_CMD); } @@ -2526,6 +2543,11 @@ outw(RxDisable, ioaddr + EL3_CMD); outw(TxDisable, ioaddr + EL3_CMD); +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) + /* Disable receiving 802.1q tagged frames */ + set_8021q_mode(dev, 0); +#endif + if (dev->if_port == XCVR_10base2) /* Turn off thinnet power. Green! */ outw(StopCoax, ioaddr + EL3_CMD); @@ -2776,6 +2798,50 @@ outw(new_mode, ioaddr + EL3_CMD); } +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) +/* Setup the card so that it can receive frames with an 802.1q VLAN tag. + Note that this must be done after each RxReset due to some backwards + compatibility logic in the Cyclone and Tornado ASICs */ +static void set_8021q_mode(struct net_device *dev, int enable) +{ + struct vortex_private *vp = (struct vortex_private *)dev->priv; + long ioaddr = dev->base_addr; + int old_window = inw(ioaddr + EL3_CMD); + int mac_ctrl; + + if (vp->drv_flags&IS_CYCLONE || vp->drv_flags&IS_TORNADO) { + /* cyclone and tornado chipsets can recognize 802.1q + * tagged frames and treat them correctly */ + + int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */ + if (enable) + max_pkt_size += 4; /* 802.1Q VLAN tag */ + + EL3WINDOW(3); + outw(max_pkt_size, ioaddr+Wn3_MaxPktSize); + + /* set VlanEtherType to let the hardware checksumming + treat tagged frames correctly */ + EL3WINDOW(7); + outw(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType); + } else { + /* on older cards we have to enable large frames */ + + vp->large_frames = dev->mtu > 1500 || enable; + + EL3WINDOW(3); + mac_ctrl = inw(ioaddr+Wn3_MAC_Ctrl); + if (vp->large_frames) + mac_ctrl |= 0x40; + else + mac_ctrl &= ~0x40; + outw(mac_ctrl, ioaddr+Wn3_MAC_Ctrl); + } + + EL3WINDOW(old_window); +} +#endif + /* MII transceiver control section. Read and write the MII registers using software-generated serial MDIO protocol. See the MII specifications or DP83840A data sheet
