On Mon, 03 Mar 2025 09:59:16 +0100, Steffen Trumtrar wrote: > When the L4WD0 is left enabled on startup, depending on handoff files > and its PLL settings, the DDR code might hang while waiting for the > calibration to be successful. Rework this code and cleanup the rest of > the driver a little bit while we are at it. > > Tested on an Enclustra PE1 board. > > [...] Applied, thanks! [1/5] ARM: SoCFPGA: move wait_on_timeout to generic https://git.pengutronix.de/cgit/barebox/commit/?id=5080f1eae33d (link may not be stable) [2/5] ARM: SoCFPGA: arria10-sdram: cleanup emif_clear https://git.pengutronix.de/cgit/barebox/commit/?id=7d639315b48c (link may not be stable) [3/5] ARM: SoCFPGA: arria10-sdram: cleanup emif_reset https://git.pengutronix.de/cgit/barebox/commit/?id=41ec8cbd8bfb (link may not be stable) [4/5] ARM: SoCFPGA: arria10-sdram: remove workaround https://git.pengutronix.de/cgit/barebox/commit/?id=da158a7fd07b (link may not be stable) [5/5] ARM: SoCFPGA: arria10-sdram: cleanup ddr_setup https://git.pengutronix.de/cgit/barebox/commit/?id=c97ef53a7eae (link may not be stable) Best regards, -- Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>