When the L4WD0 is left enabled on startup, depending on handoff files
and its PLL settings, the DDR code might hang while waiting for the
calibration to be successful. Rework this code and cleanup the rest of
the driver a little bit while we are at it.
Tested on an Enclustra PE1 board.
Signed-off-by: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
---
Steffen Trumtrar (5):
ARM: SoCFPGA: move wait_on_timeout to generic
ARM: SoCFPGA: arria10-sdram: cleanup emif_clear
ARM: SoCFPGA: arria10-sdram: cleanup emif_reset
ARM: SoCFPGA: arria10-sdram: remove workaround
ARM: SoCFPGA: arria10-sdram: cleanup ddr_setup
arch/arm/mach-socfpga/arria10-sdram.c | 196 ++++++----------------------------
arch/arm/mach-socfpga/arria10-xload.c | 16 ---
include/mach/socfpga/generic.h | 16 +++
3 files changed, 46 insertions(+), 182 deletions(-)
---
base-commit: 2afd1a809f1a41f1dd42b95c2bc0ae74853b475b
change-id: 20250303-v2025-02-0-topic-socfpga-arria10-bf2ce013ebcb
Best regards,
--
Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
