Some ARMv7 cores like the Cortex-R5 do not have a VBAR register for
setting up the vector table. This patch disables the vector table
setup specifically for the Cortex-R5.
Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
arch/arm/cpu/no-mmu.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/cpu/no-mmu.c b/arch/arm/cpu/no-mmu.c
index be3cfaf12b..c4ef5d1f9d 100644
--- a/arch/arm/cpu/no-mmu.c
+++ b/arch/arm/cpu/no-mmu.c
@@ -19,9 +19,26 @@
#include <asm/system_info.h>
#include <debug_ll.h>
#include <asm/sections.h>
+#include <asm/cputype.h>
#define __exceptions_size (__exceptions_stop - __exceptions_start)
+static bool has_vbar(void)
+{
+ u32 mainid;
+
+ __asm__ __volatile__(
+ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n"
+ : "=r" (mainid)
+ :
+ : "memory");
+
+ if ((mainid & 0xfff0) == ARM_CPU_PART_CORTEX_R5)
+ return false;
+
+ return true;
+}
+
static int nommu_v7_vectors_init(void)
{
void *vectors;
@@ -30,6 +47,9 @@ static int nommu_v7_vectors_init(void)
if (cpu_architecture() < CPU_ARCH_ARMv7)
return 0;
+ if (!has_vbar())
+ return 0;
+
/*
* High vectors cannot be re-mapped, so we have to use normal
* vectors
--
2.39.5
