Cache flushing functions expect virtual addresses, so make sure those
are properly converted from the physical ones in dma_sync_single_for_*.
QEMU doesn't care as it ignores cache instructions, but without such
change this code would result in TLB exceptions on real hardware.
Signed-off-by: Denis Orlov <denorl2009@xxxxxxxxx>
---
arch/mips/lib/dma-default.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/lib/dma-default.c b/arch/mips/lib/dma-default.c
index 48176e5d28..f6c750b8ac 100644
--- a/arch/mips/lib/dma-default.c
+++ b/arch/mips/lib/dma-default.c
@@ -30,11 +30,15 @@ static inline void __dma_sync_mips(unsigned long addr, size_t size,
void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
enum dma_data_direction dir)
{
- __dma_sync_mips(address, size, dir);
+ unsigned long virt = (unsigned long)phys_to_virt(address);
+
+ __dma_sync_mips(virt, size, dir);
}
void dma_sync_single_for_device(dma_addr_t address, size_t size,
enum dma_data_direction dir)
{
- __dma_sync_mips(address, size, dir);
+ unsigned long virt = (unsigned long)phys_to_virt(address);
+
+ __dma_sync_mips(virt, size, dir);
}
--
2.30.2
