A mux in a composite clk may implement a set_rate callback which
in the mux results in reparenting the composite clk. clk_set_rate()
is called on the mux inside the composite clk, not on the composite
clk itself. Only the latter has the correct enable_count though,
so transfer the enable_count to the mux before calling its set_rate
op.
Without this patch the clk frameworks sees the enable_count from
the mux (which is 0), so the new parent will never be enabled, even
if the composite clk is enabled.
The wrong behaviour was observed on a RK3568 board:
barebox@Radxa ROCK3 Model A:/ clk_dump cclk_emmc
xin24m (rate 24000000, enable_count: 9, enabled)
pll_gpll (rate 1188000000, enable_count: 1, enabled)
gpll (rate 1188000000, enable_count: 5, always enabled)
gpll_200m (rate 198000000, enable_count: 5, enabled)
cclk_emmc (rate 198000000, enable_count: 1, enabled)
emmc_drv (rate 99000000, enable_count: 0, always enabled)
emmc_sample (rate 99000000, enable_count: 0, always enabled)
barebox@Radxa ROCK3 Model A:/ clk_set_rate cclk_emmc 50000000
barebox@Radxa ROCK3 Model A:/ clk_dump cclk_emmc
xin24m (rate 24000000, enable_count: 9, enabled)
pll_cpll (rate 1000000000, enable_count: 1, enabled)
cpll (rate 1000000000, enable_count: 2, always enabled)
cpll_50m (rate 50000000, enable_count: 0, enabled)
cclk_emmc (rate 50000000, enable_count: 1, enabled)
emmc_drv (rate 25000000, enable_count: 0, always enabled)
emmc_sample (rate 25000000, enable_count: 0, always enabled)
After the reparenting cclk_emmc has an enable count of 1, but its parent
cpll_50m has an enable count of 0 which must not happen.
Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
drivers/clk/clk-composite.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 45dec790d7..454bfaeb0c 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -89,8 +89,16 @@ static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
if (!(hw->clk.flags & CLK_SET_RATE_NO_REPARENT) &&
mux_clk &&
- mux_clk->ops->set_rate)
+ mux_clk->ops->set_rate) {
+ /*
+ * We'll call set_rate on the mux clk which in turn results
+ * in reparenting the mux clk. Make sure the enable count
+ * (which is stored in the composite clk, not the mux clk)
+ * is transferred correctly.
+ */
+ mux_clk->enable_count = hw->clk.enable_count;
return mux_clk->ops->set_rate(clk_to_clk_hw(mux_clk), rate, parent_rate);
+ }
return 0;
}
--
2.30.2
