The mux/div/gate clks are never registered with the clk framework,
so names are normally not necessary. At least the mux clk might
end up in a call to clk_set_parent() though. This happens when a
mux shall change its rate and then reparents to the most suitable
parent. To get a better clue which being reparented there give the
mux a name and while at it give the other clocks names as well.
Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
drivers/clk/rockchip/clk.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 6e7bba414f..5c074f526a 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -59,6 +59,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
mux->width = mux_width;
mux->flags = mux_flags;
mux->lock = lock;
+ mux->hw.clk.name = basprintf("%s.mux", name);
mux->hw.clk.ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
: &clk_mux_ops;
}
@@ -74,6 +75,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
gate->reg = base + gate_offset;
gate->shift = gate_shift;
gate->lock = lock;
+ gate->hw.clk.name = basprintf("%s.gate", name);
gate->hw.clk.ops = &clk_gate_ops;
}
@@ -93,6 +95,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
div->width = div_width;
div->lock = lock;
div->table = div_table;
+ div->hw.clk.name = basprintf("%s.div", name);
div->hw.clk.ops = (div_flags & CLK_DIVIDER_READ_ONLY)
? &clk_divider_ro_ops
: &clk_divider_ops;
--
2.30.2
