To make deep-probe work properly, we need clock support be registered as
driver to related device.
Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
---
arch/arm/boards/raspberry-pi/rpi-common.c | 73 -------------------
drivers/clk/Makefile | 1 +
drivers/clk/clk-rpi.c | 85 +++++++++++++++++++++++
3 files changed, 86 insertions(+), 73 deletions(-)
create mode 100644 drivers/clk/clk-rpi.c
diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c
index 247d12467a..dfd5543405 100644
--- a/arch/arm/boards/raspberry-pi/rpi-common.c
+++ b/arch/arm/boards/raspberry-pi/rpi-common.c
@@ -45,12 +45,6 @@ struct msg_get_arm_mem {
u32 end_tag;
};
-struct msg_get_clock_rate {
- struct bcm2835_mbox_hdr hdr;
- struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
- u32 end_tag;
-};
-
struct msg_get_board_rev {
struct bcm2835_mbox_hdr hdr;
struct bcm2835_mbox_tag_get_board_rev get_board_rev;
@@ -80,22 +74,6 @@ static int rpi_get_arm_mem(u32 *size)
return 0;
}
-static struct clk *rpi_register_firmware_clock(u32 clock_id, const char *name)
-{
- BCM2835_MBOX_STACK_ALIGN(struct msg_get_clock_rate, msg);
- int ret;
-
- BCM2835_MBOX_INIT_HDR(msg);
- BCM2835_MBOX_INIT_TAG(&msg->get_clock_rate, GET_CLOCK_RATE);
- msg->get_clock_rate.body.req.clock_id = clock_id;
-
- ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
- if (ret)
- return ERR_PTR(ret);
-
- return clk_fixed(name, msg->get_clock_rate.body.resp.rate_hz);
-}
-
static void rpi_set_usbethaddr(void)
{
BCM2835_MBOX_STACK_ALIGN(struct msg_get_mac_address, msg);
@@ -343,57 +321,6 @@ static int rpi_postcore_init(void)
}
postcore_initcall(rpi_postcore_init);
-static int rpi_clock_init(void)
-{
- struct clk *clk;
-
- clk = rpi_register_firmware_clock(BCM2835_MBOX_CLOCK_ID_EMMC,
- "bcm2835_mci0");
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
- clkdev_add_physbase(clk, 0x20300000, NULL);
- clkdev_add_physbase(clk, 0x3f300000, NULL);
-
- clk = rpi_register_firmware_clock(BCM2835_MBOX_CLOCK_ID_CORE,
- "bcm2835_sdhost");
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
- clkdev_add_physbase(clk, 0x20202000, NULL);
- clkdev_add_physbase(clk, 0x3f202000, NULL);
-
- return 0;
-}
-postconsole_initcall(rpi_clock_init);
-
-static int rpi_console_clock_init(void)
-{
- struct clk *clk;
-
- clk = clk_fixed("apb_pclk", 0);
- clk_register_clkdev(clk, "apb_pclk", NULL);
-
- clk = clk_fixed("uart0-pl0110", 48 * 1000 * 1000);
- clk_register_clkdev(clk, NULL, "uart0-pl0110");
- clkdev_add_physbase(clk, BCM2835_PL011_BASE, NULL);
- clkdev_add_physbase(clk, BCM2836_PL011_BASE, NULL);
-
- clk = rpi_register_firmware_clock(BCM2835_MBOX_CLOCK_ID_CORE,
- "uart1-8250");
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
- clkdev_add_physbase(clk, BCM2835_MINIUART_BASE, NULL);
- clkdev_add_physbase(clk, BCM2836_MINIUART_BASE, NULL);
-
- clk = clk_fixed("bcm2835-cs", 1 * 1000 * 1000);
- clk_register_clkdev(clk, NULL, "bcm2835-cs");
-
- return 0;
-}
-postcore_initcall(rpi_console_clock_init);
-
static int rpi_env_init(void)
{
struct stat s;
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 499df2fe39..9675d45dc9 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_LAYERSCAPE) += clk-qoric.o
obj-y += analogbits/
obj-$(CONFIG_CLK_SIFIVE) += sifive/
obj-$(CONFIG_SOC_STARFIVE) += starfive/
+obj-$(CONFIG_MACH_RPI_COMMON) += clk-rpi.o
diff --git a/drivers/clk/clk-rpi.c b/drivers/clk/clk-rpi.c
new file mode 100644
index 0000000000..59ae8e59ba
--- /dev/null
+++ b/drivers/clk/clk-rpi.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+
+#include <mach/core.h>
+#include <mach/mbox.h>
+#include <mach/platform.h>
+#include <dt-bindings/clock/bcm2835.h>
+
+#define BCM2711_CLOCK_END (BCM2711_CLOCK_EMMC2 + 1)
+
+static struct clk *clks[BCM2711_CLOCK_END];
+static struct clk_onecell_data clk_data;
+
+struct msg_get_clock_rate {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
+ u32 end_tag;
+};
+
+static struct clk *rpi_register_firmware_clock(u32 clock_id, const char *name)
+{
+ BCM2835_MBOX_STACK_ALIGN(struct msg_get_clock_rate, msg);
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_clock_rate, GET_CLOCK_RATE);
+ msg->get_clock_rate.body.req.clock_id = clock_id;
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return clk_fixed(name, msg->get_clock_rate.body.resp.rate_hz);
+}
+
+static int bcm2835_cprman_probe(struct device_d *dev)
+{
+ struct clk *clk_cs;
+
+ clks[BCM2835_CLOCK_EMMC] =
+ rpi_register_firmware_clock(BCM2835_MBOX_CLOCK_ID_EMMC,
+ "bcm2835_mci0");
+ if (IS_ERR(clks[BCM2835_CLOCK_EMMC]))
+ return PTR_ERR(clks[BCM2835_CLOCK_EMMC]);
+
+ clks[BCM2835_CLOCK_VPU] =
+ rpi_register_firmware_clock(BCM2835_MBOX_CLOCK_ID_CORE,
+ "vpu");
+ if (IS_ERR(clks[BCM2835_CLOCK_VPU]))
+ return PTR_ERR(clks[BCM2835_CLOCK_VPU]);
+
+ clks[BCM2835_CLOCK_UART] = clk_fixed("uart0-pl0110", 48 * 1000 * 1000);
+ clk_register_clkdev(clks[BCM2835_CLOCK_UART], NULL, "uart0-pl0110");
+
+ clk_cs = clk_fixed("bcm2835-cs", 1 * 1000 * 1000);
+ clk_register_clkdev(clk_cs, NULL, "bcm2835-cs");
+
+ clk_data.clks = clks;
+ clk_data.clk_num = BCM2711_CLOCK_END;
+ of_clk_add_provider(dev->device_node, of_clk_src_onecell_get, &clk_data);
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id bcm2835_cprman_dt_ids[] = {
+ {
+ .compatible = "brcm,bcm2835-cprman",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d bcm2835_cprman_driver = {
+ .probe = bcm2835_cprman_probe,
+ .name = "bcm2835-cprman",
+ .of_compatible = DRV_OF_COMPAT(bcm2835_cprman_dt_ids),
+};
+core_platform_driver(bcm2835_cprman_driver);
--
2.30.2
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